PIC12F1840-I/P Microchip Technology, PIC12F1840-I/P Datasheet - Page 147

• Manufacturer Part Number: PIC12F1840-I/P
• Description: 7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 PDI
• Manufacturer: Microchip Technology

Specifications of PIC12F1840-I/P

• Processor Series: PIC12F
• Core: PIC
• Program Memory Type: Flash
• Program Memory Size: 7 KB
• Data Ram Size: 256 B
• Interface Type: MI2C, SPI, EUSART
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-8
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 18-1:
REGISTER 18-1:
 2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6-4
bit 3
bit 2
bit 1
bit 0
Note 1:
SRCLK
R/W-0/0
SRLEN
111
110
101
100
011
010
001
000
Set only, always reads back ‘0’.
SRLEN: SR Latch Enable bit
1 = SR Latch is enabled
0 = SR Latch is disabled
SRCLK<2:0>: SR Latch Clock Divider bits
000 = Generates a 1 F
001 = Generates a 1 F
010 = Generates a 1 F
011 = Generates a 1 F
100 = Generates a 1 F
101 = Generates a 1 F
110 = Generates a 1 F
111 = Generates a 1 F
SRQEN: SR Latch Q Output Enable bit
If SRLEN = 1:
If SRLEN = 0:
SR Latch is disabled
SRNQEN: SR Latch Q Output Enable bit
If SRLEN = 1:
If SRLEN = 0:
SRPS: Pulse Set Input of the SR Latch bit
1 = Pulse set input for 1 Q-clock period
0 = No effect on set input.
SRPR: Pulse Reset Input of the SR Latch bit
1 = Pulse reset input for 1 Q-clock period
0 = No effect on Reset input.
Divider
SRCLK FREQUENCY TABLE
512
256
128
SRCLK2
R/W-0/0
64
32
16
8
4
1 = Q is present on the SRQ pin
0 = External Q output is disabled
1 = Q is present on the SRnQ pin
0 = External Q output is disabled
SR Latch is disabled
SRCON0: SR LATCH CONTROL 0 REGISTER
F
OSC
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
62.5 kHz
125 kHz
250 kHz
500 kHz
1 MHz
2 MHz
4 MHz
8 MHz
SRCLK1
R/W-0/0
= 32 MHz
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
wide pulse every 4th F
wide pulse every 8th F
wide pulse every 16th F
wide pulse every 32nd F
wide pulse every 64th F
wide pulse every 128th F
wide pulse every 256th F
wide pulse every 512th F
F
SRCLK0
OSC
R/W-0/0
1.25 MHz
39.0 kHz
78.1 kHz
2.5 MHz
156 kHz
313 kHz
625 kHz
Preliminary
5 MHz
= 20 MHz
(1)
(1)
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
S = Bit is set only
R/W-0/0
SRQEN
OSC
OSC
OSC
OSC
F
OSC
OSC
OSC
OSC
OSC
cycle clock
cycle clock
31.3 kHz
62.5 kHz
125 kHz
250 kHz
500 kHz
cycle clock
cycle clock
1 MHz
2 MHz
4 MHz
cycle clock
cycle clock
cycle clock
cycle clock
= 16 MHz
SRNQEN
R/W-0/0
PIC12(L)F1840
F
OSC
31.25 kHz
7.81 kHz
15.6 kHz
62.5 kHz
125 kHz
250 kHz
500 kHz
1 MHz
= 4 MHz
R/S-0/0
SRPS
DS41441B-page 147
F
OSC
1.95 kHz
3.90 kHz
7.81 kHz
15.6 kHz
31.3 kHz
62.5 kHz
125 kHz
250 kHz
R/S-0/0
SRPR
= 1 MHz
bit 0