PIC12F1840-I/P Microchip Technology, PIC12F1840-I/P Datasheet - Page 154

• Manufacturer Part Number: PIC12F1840-I/P
• Description: 7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 PDI
• Manufacturer: Microchip Technology

Specifications of PIC12F1840-I/P

• Processor Series: PIC12F
• Core: PIC
• Program Memory Type: Flash
• Program Memory Size: 7 KB
• Data Ram Size: 256 B
• Interface Type: MI2C, SPI, EUSART
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-8
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC12(L)F1840
19.3
A selectable amount of separation voltage can be
added to the input pins of each comparator to provide a
hysteresis function to the overall operation. Hysteresis
is enabled by setting the C1HYS bit of the CM1CON0
register.
See Section 30.0 “Electrical Specifications” for
more information.
19.4
The output resulting from a comparator operation can
be used as a source for gate control of Timer1. See
Section 21.6 “Timer1 Gate” for more information.
This feature is useful for timing the duration or interval
of an analog event.
It is recommended that the comparator output be syn-
chronized to Timer1. This ensures that Timer1 does not
increment while a change in the comparator is occur-
ring.
19.4.1
The output from comparator C1 can be synchronized
with Timer1 by setting the C1SYNC bit of the
CM1CON0 register.
Once enabled, the comparator output is latched on the
falling edge of the Timer1 source clock. If a prescaler is
used with Timer1, the comparator output is latched after
the prescaling function. To prevent a race condition, the
comparator output is latched on the falling edge of the
Timer1 clock source and Timer1 increments on the
rising edge of its clock source. See the Comparator
Block Diagram
Diagram
DS41441B-page 154
Comparator Hysteresis
Timer1 Gate Operation
(Figure
COMPARATOR OUTPUT
SYNCHRONIZATION
(Figure
21-1) for more information.
19-2) and the Timer1 Block
Preliminary
19.5
An interrupt can be generated upon a change in the
output value of the comparator for each comparator, a
rising edge detector and a Falling edge detector are
present.
When either edge detector is triggered and its associ-
ated enable bit is set (C1INTP and/or C1INTN bits of
the CM1CON1 register), the Corresponding Interrupt
Flag bit (C1IF bit of the PIR2 register) will be set.
To enable the interrupt, you must set the following bits:
• C1ON, C1POL and C1SP bits of the CM1CON0
• C1IE bit of the PIE2 register
• C1INTP bit of the CM1CON1 register (for a rising
• C1INTN bit of the CM1CON1 register (for a falling
• PEIE and GIE bits of the INTCON register
The associated interrupt flag bit, C1IF bit of the PIR2
register, must be cleared in software. If another edge is
detected while this flag is being cleared, the flag will still
be set at the end of the sequence.
19.6
Configuring the C1PCH<1:0> bits of the CM1CON1
register directs an internal voltage reference or an
analog pin to the non-inverting input of the comparator:
• C1IN+ analog pin
• DAC
• FVR (Fixed Voltage Reference)
• V
See
for more information on the Fixed Voltage Reference
module.
See
(DAC) Module”
signal.
Any time the comparator is disabled (C1ON = 0), all
comparator inputs are disabled.
register
edge detection)
edge detection)
Note:
SS
Section 14.0 “Fixed Voltage Reference (FVR)”
Section 17.0 “Digital-to-Analog
(Ground)
Comparator Interrupt
Comparator Positive Input
Selection
Although a comparator is disabled, an
interrupt can be generated by changing
the output polarity with the C1POL bit of
the CM1CON0 register, or by switching
the comparator on or off with the C1ON bit
of the CM1CON0 register.
for more information on the DAC input
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