PIC12F1840-I/P Microchip Technology, PIC12F1840-I/P Datasheet - Page 302

• Manufacturer Part Number: PIC12F1840-I/P
• Description: 7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 PDI
• Manufacturer: Microchip Technology

Specifications of PIC12F1840-I/P

• Processor Series: PIC12F
• Core: PIC
• Program Memory Type: Flash
• Program Memory Size: 7 KB
• Data Ram Size: 256 B
• Interface Type: MI2C, SPI, EUSART
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-8
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC12(L)F1840
REGISTER 27-2:
TABLE 27-3:
DS41441B-page 302
ANSELA
CPSCON0
CPSCON1
INTCON
OPTION_REG
T1CON
TRISA
Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the CPS module.
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-2
bit 1-0
Name
U-0
—
TMR1CS1 TMR1CS0
Unimplemented: Read as ‘0’
CPSCH<1:0>: Capacitive Sensing Channel Select bits
If CPSON = 0:
If CPSON = 1:
WPUEN
CPSON
SUMMARY OF REGISTERS ASSOCIATED WITH CAPACITIVE SENSING
Bit 7
GIE
—
—
—
These bits are ignored. No channel is selected.
U-0
00 = channel 0, (CPS0)
01 = channel 1, (CPS1)
10 = channel 2, (CPS2)
11 = channel 3, (CPS3)
—
CPSCON1: CAPACITIVE SENSING CONTROL REGISTER 1
INTEDG
CPSRM
PEIE
Bit 6
—
—
—
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U-0
—
T1CKPS1
TMR0CS
TMR0IE
TRISA5
Bit 5
—
—
—
T1CKPS0
U-0
TMR0SE
Preliminary
—
TRISA4
ANSA4
INTE
Bit 4
—
—
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
CPSRNG1 CPSRNG0
T1OSCEN
TRISA3
IOCIE
Bit 3
PSA
U-0
—
—
—
T1SYNC
TMR0IF
TRISA2
ANSA2
Bit 2
PS2
—
U-0
—
CPSOUT
CPSCH1
TRISA1
ANSA1
Bit 1
INTF
PS1
 2011 Microchip Technology Inc.
—
R/W-0/0
TMR1ON
CPSCH0
TRISA0
CPSCH<1:0>
ANSA0
T0XCS
IOCIF
Bit 0
PS0
R/W-0/0
Register
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83
bit 0