21150-AB Intel Corporation, 21150-AB Datasheet
21150-AB
Specifications of 21150-AB
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21150-AB Summary of contents
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... Hardware disable control, to permit use of an external arbiter 1. For 21150-AB and later revisions only. The 21150-AA does not implement this feature. Notice: This document contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design ...
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... Intel may make changes to specifications and product descriptions at any time, without notice. The 21150 PCI-to-PCI Bridge may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. ...
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... Prefetchable Read Transactions ............................................................37 4.6.2 Nonprefetchable Read Transactions......................................................37 4.6.3 Read Prefetch Address Boundaries .......................................................38 4.6.4 Delayed Read Requests ........................................................................38 4.6.5 Delayed Read Completion with Target...................................................39 4.6.6 Delayed Read Completion on Initiator Bus ............................................39 4.7 Configuration Transactions .................................................................................42 4.7.1 Type 0 Access to the 21150 ...................................................................43 4.7.2 Type 1 to Type 0 Translation..................................................................44 4.7.3 Type 1 to Type 1 Forwarding .................................................................45 4.7.4 Special Cycles ........................................................................................46 Preliminary Datasheet 21150 iii ...
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... Transactions Governed by Ordering Rules ......................................................... 65 6.2 General Ordering Guidelines .............................................................................. 66 6.3 Ordering Rules .................................................................................................... 66 6.4 Data Synchronization .......................................................................................... 68 7.0 Error Handling .................................................................................................................. 69 7.1 Address Parity Errors .......................................................................................... 69 7.2 Data Parity Errors................................................................................................ 70 7.2.1 Configuration Write Transactions to 21150 Configuration Space .......... 70 7.2.2 Read Transactions ................................................................................. 70 7.2.3 Delayed Write Transactions ................................................................... 71 7.2.4 Posted Write Transactions ..................................................................... 73 7.3 Data Parity Error Reporting Summary ................................................................ 74 7.4 System Error (SERR#) Reporting ....................................................................... 78 8.0 Exclusive Access ............................................................................................................. 81 8.1 Concurrent Locks ...
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... Prefetchable Memory Base Address Upper 32 Bits Register— Offset 28h..........................................................................................................116 15.1.24 Prefetchable Memory Limit Address Upper 32 Bits Register— Offset 2Ch .........................................................................................................117 15.1.25 I/O Base Address Upper 16 Bits Register—Offset 30h ........................117 15.1.26 I/O Limit Address Upper 16 Bits Register—Offset 32h ........................118 Preliminary Datasheet 21150 v ...
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... JTAG Signal Pins .............................................................................................. 135 16.3 Test Access Port Controller .............................................................................. 135 16.4 Instruction Register ........................................................................................... 136 16.5 Bypass Register ................................................................................................ 136 16.6 Boundary-Scan Register ................................................................................... 136 16.6.1 Boundary-Scan Register Cells ............................................................. 137 16.6.2 21150 Boundary-Scan Order ............................................................... 137 16.7 Initialization ....................................................................................................... 141 17.0 Electrical Specifications ................................................................................................. 143 17.1 PCI Electrical Specification Conformance......................................................... 143 17.2 Absolute Maximum Ratings .............................................................................. 143 17.3 DC Specifications .............................................................................................. 144 17 ...
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... Figures 1 21150 on the System Board.................................................................................. 2 2 21150 with Option Cards....................................................................................... 3 3 21150 on the System Board.................................................................................. 4 4 21150 Downstream Data Path .............................................................................. 5 5 21150 Pin Assignment ........................................................................................19 6 Flow-Through Posted Memory Write Transaction...............................................31 7 Downstream Delayed Write Transaction.............................................................34 8 Multiple Memory Write Transactions Posted and Initiated as Fast Back-to-Back Transactions on the Target Bus ...
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... Device Number to IDSEL s_ad Pin Mapping ...................................................... 45 21 21150 Response to Delayed Write Target Termination ...................................... 50 22 21150 Response to Posted Write Target Termination ........................................ 51 23 21150 Response to Delayed Read Target Termination ...................................... 51 24 Summary of Transaction Ordering ...................................................................... 66 25 Setting the Primary Interface Detected Parity Error Bit ....................................... 74 26 Setting the Secondary Interface Detected Parity Error Bit ...
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... PCI devices or more PCI option card slots than a single PCI bus can support. system board. Each 21150 that is added to the board creates a new PCI bus that provides support for the additional PCI slots or devices Option card designers can use the 21150 to implement multiple-device PCI option cards. Without a PCI-to-PCI bridge, PCI loading rules would limit option cards to one device ...
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... Figure 1. 21150 on the System Board Memory and Cache SCSI 2 CPU 21150 Core Graphics Logic PCI Bus 21150 ISA or LAN EISA ISA or EISA Bus Bridge Support PCI Option Slots PCI Bus PCI Option Slots ISA or EISA Option Slots PCI Bus Chip ...
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... Figure 2. 21150 with Option Cards 21150 Note: 1.1 Architecture The 21150 internal architecture consists of the following major functions: • PCI interface control logic for the primary and secondary PCI interfaces • Data path and data path control logic • Configuration register and configuration control logic • ...
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... Figure 3. 21150 on the System Board Secondary Arbiter Clocks and Reset Primary Request and Grant Table 1. 21150 Functional Blocks (Sheet Function Blocks Primary and Secondary Control Primary-to-Secondary Data Path 4 Secondary Data Secondary Control Secondary Arbiter Primary and Secondary Control ...
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... Read data queue To prevent deadlocks and to maintain data coherency, a set of ordering rules is imposed on the forwarding of posted and delayed transactions across the 21150. The queue structure, along with the order in which the transactions in the queues are initiated and completed, supports these ordering requirements. ...
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... The amount of read data per transaction depends on the amount of space in the queue and disconnect boundaries. Read data for up to three transactions, subject to the burst size of the read transactions and available queue space, can be stored. The read data queue for the 21150 consists of 72 bytes in each direction. 6 ...
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... Signal Pins This chapter provides detailed descriptions of the 21150 signal pins, grouped by function. Table 2 describes the signal pin functional groups, and the following sections describe the signals in each group. Table 2. Signal Pins Function Primary PCI bus interface signal pins Secondary PCI bus ...
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... TS transaction, the initiator drives write data, or the target drives read data, on p_ad<31:0>. When the primary PCI bus is idle, the 21150 drives p_ad to a valid logic level when p_gnt_l is asserted. Primary PCI interface command/byte enables. These signals are a multiplexed command field and byte enable field. During the address phase or phases of a transaction, the initiator drives the transaction type on p_cbe_l< ...
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... The 21150 samples p_lock_l as a target and can I propagate the lock across to the secondary bus. The 21150 does not drive p_lock_l as an initiator; that is, the 21150 does not propagate locked transactions upstream. When released by an initiator, p_lock_l is driven to a deasserted state for one cycle and then is sustained by an external pull-up resistor ...
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... Primary PCI bus GNT#. When asserted, p_gnt_lindicates to the 21150 that access to the primary bus is granted. The 21150 can start a transaction on the primary bus when the bus I is idle and p_gnt_l is asserted. When the 21150 has not requested use of the bus and p_gnt_l is asserted, the 21150 must drive p_ad, and p_par to valid logic levels ...
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... TS transaction, the initiator drives write data, or the target drives read data, on s_ad<31:0>. When the secondary PCI bus is idle, the 21150 drives s_ad to a valid logic level when its secondary bus grant is asserted. Secondary PCI interface command/byte enables. These signals are a multiplexed command field and byte enable field. ...
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... STS s_devsel_l initiator of a transaction on the secondary bus, the 21150 looks for the assertion of s_devsel_l within five cycles of s_frame_l assertion; otherwise, the 21150 terminates the transaction with a master abort. When the secondary bus is idle, s_devsel_l is driven to a deasserted state for one cycle and then is sustained by an external pull-up resistor ...
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... Type Description Secondary PCI interface LOCK#. Signal s_lock_l is deasserted during the first address phase of a transaction and is asserted one clock cycle later by the 21150 when it is propagating a locked transaction downstream. The 21150 STS does not propagate locked transactions upstream. The 21150 continues to assert s_lock_l until the address phase of the next locked transaction, or until the lock is released ...
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... PCI bus. All primary PCI inputs are sampled on the rising edge of p_clk, and all primary PCI outputs are driven I from the rising edge of p_clk. Frequencies supported by the 21150 range from 0 MHz to 33 MHz MHz to 66 MHz for a 66 MHz capable 21150. Preliminary Datasheet ...
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... Reset Signals Signal Name 1 bpcce p_rst_l s_rst_l 1. For 21150-AB and later revisions only Preliminary Datasheet Secondary interface PCI CLK. Provides timing for all transactions on the secondary PCI bus. All secondary PCI inputs are sampled on the rising edge of s_clk, and all I secondary PCI outputs are driven from the rising edge of s_clk ...
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... Signal s_vio is tied to 3.3 V only when all the devices on the secondary bus use 3.3-V signaling levels. Configure 66 MHz operation. This input only pin is used to specify if the 21150 is capable of running at 66 MHz. If the pin I is tied high, then the device can be run at 66 MHz. If the pin is tied low, then the 21150 can only function under the 33 MHz PCI specification ...
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... JTAG boundary-scan clock. Signal tck is the clock controlling I the JTAG logic. JTAG TAP reset. When asserted low, the TAP controller is asynchronously forced to enter a reset state, which in turn I asynchronously initializes other test logic. An unterminated trst_l produces the same result were driven high. 21150 17 ...
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...
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... Pin Assignments This chapter describes the 21150 pins. It provides numeric and alphabetic lists of the pins and includes a diagram showing 21150 pin assignment. Figure 5 shows the 21150 pins. Figure 5. 21150 Pin Assignment vdd req_l<1> req_l<2> req_l<3> 5 req_l<4> req_l<5> req_l<6> req_l<7> req_l<8> 10 gnt_l<0> ...
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... Numeric Pin Assignment Table 13 lists the 21150 pins in numeric order, showing the name, number, and signal type of each pin. Table 12 defines the signal type abbreviations. Table 12. Signal Types Signal Type STS OD 20 Description Standard input only. Standard output only. ...
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... P vdd 27 TS p_ad<24> p_cbe_l<3> p_idsel 30 O vss 31 P p_ad<23> p_ad<22> vdd 34 P p_ad<21> P_ad<20> vss 21150 Pin Type Number ...
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... Table 13. Numeric Pin Assignments (Sheet Pin p_ad<19> p_ad<18> vdd p_ad<17> p_ad<16> vss p_cbe_l<2> p_frame_l vdd p_irdy_l p_trdy_l p_devsel_l p_stop_l vss p_lock_l p_perr_l p_serr_l p_par vdd p_cbe_l<1> p_ad<15> vss p_ad<14> p_ad<13> vdd p_ad<12> p_ad<11> vss p_ad<10> p_m66ena vdd vss vdd vss p_ad< ...
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... Pertains to the 21150-AB and later revisions only. For the 21150-AA, this pin was vss. 2. nc–Do not connect these pins on the board. Preliminary Datasheet Pin Type Pin Number 147 TS vdd ...
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... Alphabetic Pin Assignment Table 14 lists the 21150 pins in alphabetic order, showing the name, number, and signal type of each pin. Table 12 defines the signal type abbreviations. Table 14. Alphabetic Pin Assignments. Pin 1 bpcce config66 s_m66ena p_m66ena gpio<0> gpio<1> gpio<2> gpio<3> msk_in p_ad< ...
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... TS s_req_l<3> 204 TS s_req_l<4> 206 TS s_req_l<5> 149 TS s_req_l<6> 167 TS s_req_l<7> 180 TS s_req_l<8> 194 TS s_rst_l 23 O s_serr_l 21 I s_stop_l 29 O s_trdy_l 21150 Pin Type Number 175 STS 179 STS ...
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... Pertains to the 21150-AB and later revisions only. For the 21150-AA, this pin was vss. 2. nc–Do not connect these pins on the board. 26 (Sheet Pin Type Pin Number 135 I vdd ...
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... As indicated in Table • The 21150 never initiates a PCI transaction with a reserved command code and target, the 21150 ignores reserved command codes. • The 21150 never initiates an interrupt acknowledge transaction and target, the 21150 ignores interrupt acknowledge transactions. Interrupt acknowledge transactions are expected to reside entirely on the primary PCI bus closest to the host bridge. • ...
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... A 32-bit address uses a single address phase. This address is driven on AD<31:0>, and the bus command is driven on C/BE#<3:0>. The 21150 supports the linear increment address mode only, which is indicated when the low 2 address bits are equal either of the low 2 address bits is nonzero, the 21150 automatically disconnects the transaction after the first data transfer. 4.2.2 ...
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... FRAME# is deasserted and both TRDY# and IRDY# are asserted, or when IRDY# and STOP# are asserted. See transaction termination. Depending on the command type, the 21150 can support multiple data phase PCI transactions. For a detailed description of how the 21150 imposes disconnect boundaries, see description of write address boundaries and boundaries ...
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... This enables the 21150 to accept write data without obtaining access to the target bus. The 21150 can accept 1 Dword of write data every PCI clock cycle; that is, no target wait states are inserted. This write data is stored in internal posted write buffers and is subsequently delivered to the target ...
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... The target returns a target abort (the 21150 discards remaining write data). • The master latency timer expires, and the 21150 no longer has the target bus grant (the 21150 starts another transaction to deliver remaining write data). Section 4.8.3.2 provides detailed information about how the 21150 responds to target termination during posted write transactions ...
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... If the value in the cache line size register does meet the memory write and invalidate conditions, that is, the value is a nonzero power of 2 less than or equal to 16 Dwords, the 21150 returns a target disconnect to the initiator either on a cache line boundary or when the posted write buffer fills. For a cache line size of 16 Dwords, the 21150 disconnects a memory write and invalidate transaction on every cache line boundary ...
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... When the initiator repeats the same write transaction (same command, address, byte enable bits, and data), and the completed delayed transaction is at the head of the queue, the 21150 claims the access by asserting DEVSEL# and returns TRDY# to the initiator, to indicate that the write data was transferred ...
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... The 21150 imposes internal address boundaries when accepting write data. The aligned address boundaries are used to prevent the 21150 from continuing a transaction over a device address boundary and to provide an upper limit on maximum latency. The 21150 returns a target disconnect to the initiator when it reaches the aligned address boundaries under the conditions shown in 17 ...
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... Buffering Multiple Write Transactions The 21150 continues to accept posted memory write transactions as long as space for at least 1 Dword of data in the posted write data buffer remains. If the posted write data buffer fills before the initiator terminates the write transaction, the 21150 returns a target disconnect to the initiator. ...
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... Read Transactions Delayed read forwarding is used for all read transactions crossing the 21150. Delayed read transactions are treated as either prefetchable or nonprefetchable. Table 18 shows the read behavior, prefetchable or nonprefetchable, for each type of read operation. Table 18. Read Transaction Prefetching (Sheet ...
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... The amount of data that is prefetched depends on the type of transaction. The amount of prefetching may also be affected by the amount of free buffer space available in the 21150, and by any read address boundaries encountered. Prefetching should not be used for those read transactions that have side effects in the target device, that is, control and status registers, FIFOs, and so on. The target device’ ...
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... When the 21150 accepts a delayed read request, it first samples the read address, read bus command, and address parity. When IRDY# is asserted, the 21150 then samples the byte enable bits for the first data phase ...
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... For example, read data in response to a downstream read transaction initiated on the primary bus is placed in the upstream read data queue. The 21150 can accept 1 Dword of read data each PCI clock cycle; that is, no master wait states are inserted. The number of Dwords transferred during a delayed read transaction depends on the conditions given in disconnect is received from the target) ...
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... Figure 9. Nonprefetchable Delayed Read Transaction CY0 Cycle < 15ns > p_clk p_ad p_cbe_l p_frame_l p_irdy_l p_devsel_l p_trdy_l p_stop_l s_clk s_ad s_cbe_l s_frame_l s_irdy_l s_devsel_l s_trdy_l s_stop_l Figure 10 shows a prefetchable delayed read transaction. 40 CY2 CY4 CY6 CY1 CY3 CY5 CY7 Addr Addr 2 Byte Enables ...
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... In this case, the read transaction is allowed to continue until the initiator terminates the transaction, or until an aligned 4KB address boundary is reached, or until the buffer fills, whichever comes first. When the buffer empties, the 21150 reflects the stalled condition to the initiator by deasserting TRDY# until more read data is available; otherwise, the 21150 does not insert any target wait states ...
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... The 21150 also conditionally asserts p_serr_l (see The 21150 has the capability to post multiple delayed read requests maximum of three in each direction initiator starts a read transaction that matches the address and read command of a read transaction that is already queued, the current read command is not posted already contained in the delayed transaction queue ...
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... Type 0 Access to the 21150 The 21150 configuration space is accessed by a Type 0 configuration transaction on the primary interface. The 21150 configuration space cannot be accessed from the secondary bus. The 21150 responds to a Type 0 configuration transaction by asserting p_devsel_l when the following conditions are met during the address phase: • ...
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... PCI device that resides on a PCI bus other than the one where the Type 1 transaction is generated. The 21150 performs a Type 1 to Type 0 translation when the Type 1 transaction is generated on the primary bus and is intended for a device attached directly to the secondary bus. The 21150 must convert the configuration command to a Type 0 format so that the secondary bus device can respond to it. Type 1 to Type 0 translations are performed only in the downstream direction ...
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... The 21150 can assert unique address lines to be used as IDSEL signals for devices on the secondary bus, for device numbers ranging from 0 through 15. Because of electrical loading constraints of the PCI bus, more than 16 IDSEL signals should not be necessary. However, if device numbers greater than 15 are desired, some external method of generating IDSEL lines must be used, and no upper address bits are then asserted ...
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... Special cycle transactions can be generated from Type 1 configuration write transactions in either the upstream or the downstream direction. The 21150 initiates a special cycle on the target bus when a Type 1 configuration write transaction is detected on the initiating bus and the following conditions are met during the address phase: • ...
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... Master Termination Initiated by the 21150 The 21150 initiator, uses normal termination if DEVSEL# is returned by the target within five clock cycles of the 21150’s assertion of FRAME# on the target bus initiator, the 21150 terminates a transaction when the following conditions are met: • ...
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... TRDY# on the initiator bus and, for read transactions, returns FFFF FFFFh as data. When the master abort mode bit is 1, the 21150 returns target abort on the initiator bus. The 21150 also sets the signaled target abort bit in the register corresponding to the initiator bus. ...
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... When a master abort is detected in response to a posted write transaction, and the master abort mode bit is set, the 21150 also asserts p_serr_l if enabled by the SERR# enable bit in the command register and if not disabled by the device-specific p_serr_l disable bit for master abort during posted write transactions (that is, master abort mode = 1 ...
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... The 21150 makes 2 After the 21150 makes 2 21150 asserts p_serr_l if the primary SERR# enable bit is set in the command register and the implementation-specific p_serr_l disable bit for this condition is not set in the p_serr_l event disable register. The 21150 stops initiating transactions in response to that delayed write transaction ...
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... Dword. If the initial write transaction is a memory write and invalidate transaction, and a partial delivery of write data to the target is performed before a target disconnect is received, the 21150 uses the memory write command to deliver the rest of the write data because less than a cache line will be transferred in the subsequent write transaction attempt ...
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... The 21150 repeats a delayed read transaction until one of the following conditions is met: • The 21150 completes at least one data transfer. • The 21150 receives a master abort. • The 21150 receives a target abort. • ...
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... Target Retry The 21150 returns a target retry to the initiator when it cannot accept write data or return read data as a result of internal conditions. The 21150 returns a target retry to an initiator when any of the following conditions is met: • For delayed write transactions: — ...
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... The 21150 is unable to obtain delayed read data from the target or to deliver delayed write data to the target after 2 When the 21150 returns a target abort to the initiator, it sets the signaled target abort bit in the status register corresponding to the initiator interface attempts ...
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... If the I/O enable bit is not set, all I/O transactions initiated on the primary bus are ignored. To enable upstream forwarding of I/O transactions, the master enable bit must be set in the command register. If the master enable bit is not set, the 21150 ignores all I/O and memory transactions initiated on the secondary bus. Setting the master enable bit also allows upstream forwarding of memory transactions ...
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... I/O address range. Figure 15. I/O Transaction Forwarding Using Base and Limit Addresses The 21150 I/O range has a minimum granularity of 4KB and is aligned on a 4KB boundary. The maximum I/O range is 4GB in size. The I/O base register consists of an 8-bit field at configuration address 1Ch, and a 16-bit field at address 30h. The top 4 bits of the 8-bit field define bits < ...
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... All other I/O transactions initiated on the secondary bus are forwarded upstream only if they fall outside the I/O address range. When the ISA enable bit is set, devices downstream of the 21150 can have I/O space mapped into the first 256 bytes of each 1KB chunk below the 64KB boundary, or anywhere in I/O space above the 64KB boundary ...
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... If any 21150 configuration state affecting memory transaction forwarding is changed by a configuration write operation on the primary bus at the same time that memory transactions are ongoing on the secondary bus, 21150 response to the secondary bus memory transactions is not predictable. Configure the memory-mapped I/O base and limit address registers, prefetchable ...
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... Read transactions to nonprefetchable space may exhibit side effects; this space may have non-memory-like behavior. The 21150 prefetches in this space only if the memory read line or memory read multiple commands are used; transactions using the memory read command are limited to a single data transfer ...
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... Locations accessed in the prefetchable memory address range must have true memory-like behavior and must not exhibit side effects when read. This means that extra reads to a prefetchable memory location must have no side effects. The 21150 prefetches for all types of memory read commands in this address space. ...
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... Crossing the first 4GB memory boundary If the prefetchable memory space on the secondary interface resides entirely in the first 4GB of memory, both upper 32 bits registers must be set to 0. The 21150 ignores all dual address cycle transactions initiated on the primary interface and forwards all dual address transactions initiated on the secondary interface upstream ...
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... VGA mode. When the 21150 is operating in VGA mode, it forwards downstream those transactions addressing the VGA frame buffer memory and VGA I/O registers, regardless of the values of the 21150 base and limit address registers. The 21150 ignores transactions initiated on the secondary interface addressing these locations. ...
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... I/O space. Note: If both the VGA mode bit and the VGA snoop bit are set, the 21150 behaves in the same way as if only the VGA mode bit were set. ...
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...
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... Transaction Ordering To maintain data coherency and consistency, the 21150 complies with the ordering rules set forth in the PCI Local Bus Specification, Revision 2.1, for transactions crossing the bridge. This chapter describes the ordering rules that control transaction forwarding across the 21150. For a more detailed discussion of transaction ordering, see Appendix E of the PCI Local Bus Specification, Revision 2 ...
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... The acceptance of a posted memory write transaction as a target can never be contingent on the completion of a nonlocked, nonposted transaction as a master. This is true of the 21150 and must also be true of other bus agents; otherwise, a deadlock can occur. • ...
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... In this case, the read data is traveling in the same direction as the write data, and the initiator of the read transaction is on the same side of the 21150 as the target of the write transaction. The posted write transaction must complete to the target before the read data is returned to the initiator ...
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... System hardware guarantees that write buffers are flushed before interrupts are forwarded. The 21150 does not have a hardware mechanism to guarantee data synchronization for posted write transactions. Therefore, all posted write transactions must be followed by a read operation, either from the device to the location just written (or some other location along the same path), or from the device driver to one of the device registers ...
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... If the parity error response bit is set in the bridge control register, the 21150 does not claim the transaction with s_devsel_l; this may allow the transaction to terminate in a master abort. If the parity error response bit is not set, the 21150 proceeds normally and accepts the transaction directed to or across the 21150. • ...
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... The 21150 also asserts p_perr_l. If the parity error response bit is not set, the 21150 does not assert p_perr_l. • The 21150 sets the detected parity error bit in the status register, regardless of the state of the parity error response bit. 7.2.2 ...
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... STOP# is also asserted to cause a target disconnect. Two cycles after the data transfer, the 21150 also asserts PERR#. If the parity error response bit is not set, the 21150 returns a target retry and queues the transaction as usual. Signal PERR# is not asserted. In this case, the initiator repeats the transaction. • ...
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... The 21150 sets the secondary interface data parity detected bit in the secondary status register, if the secondary parity error response bit is set in the bridge control register. • The 21150 captures the parity error condition to forward it back to the initiator on the primary bus. Similarly, for upstream transactions, when the 21150 is delivering data to the target on the primary bus and p_perr_l is asserted by the target, the following events occur: • ...
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... The 21150 sets the data parity detected bit in the secondary status register, if the secondary interface parity error response bit is set in the bridge control register. • The 21150 asserts p_serr_l and sets the signaled system error bit in the status register, if all of the following conditions are met: — The SERR# enable bit is set in the command register. ...
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... Delayed write 0 Delayed write don’t care Table 26 shows setting the detected parity error bit in the secondary status register, corresponding to the secondary interface. This bit is set when the 21150 detects a parity error on the secondary interface. 74 Transaction Type Direction Downstream Downstream ...
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... This bit is set under the following conditions: • The 21150 must be a master on the primary bus. • The parity error response bit in the command register, corresponding to the primary interface, must be set. • ...
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... Table 29 shows assertion of p_perr_l. This signal is set under the following conditions: • The 21150 is either the target of a write transaction or the initiator of a read transaction on the primary bus. • The parity error response bit in the command register, corresponding to the primary interface, must be set. • ...
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... Table 30 shows assertion of s_perr_l.. This signal is set under the following conditions: • The 21150 is either the target of a write transaction or the initiator of a read transaction on the secondary bus. • The parity error response bit in the bridge control register, corresponding to the secondary interface, must be set. • ...
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... In compliance with the PCI-to-PCI Bridge Architecture Specification, the 21150 asserts p_serr_l when it detects the secondary SERR# input, s_serr_l, asserted and the SERR# forward enable bit is set in the bridge control register. In addition, the 21150 also sets the received system error bit in the secondary status register. ...
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... Master timeout on delayed transaction The device-specific p_serr_l status register reports the reason for the 21150’s assertion of p_serr_l. Most of these events have additional device-specific disable bits in the p_serr_l event disable register that make it possible to mask out p_serr_l assertion for specific events. The master timeout condition has a SERR# enable bit for that event in the bridge control register and therefore does not have a device-specific disable bit ...
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...
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... When the target resides on another PCI bus, the master must acquire not only the lock on its own PCI bus but also the lock on every bus between its bus and the target’s bus. When the 21150 detects, on the primary bus, an initial locked transaction intended for a target on the secondary bus, ...
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... When the last locked transaction is a delayed transaction, the 21150 has already completed the transaction on the secondary bus. In this case, as soon as the 21150 detects that the initiator has relinquished the p_lock_l signal by sampling it in the deasserted state while p_frame_l is deasserted, the 21150 deasserts the s_lock_l signal on the secondary bus as soon as possible ...
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... When the 21150 receives a target abort or a master abort in response to a locked posted write transaction, the 21150 cannot pass back that status to the initiator. The 21150 asserts p_serr_l when a target abort or a master abort is received during a locked posted write transaction, if the SERR# enable bit is set in the command register ...
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...
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... When the primary bus is parked at the 21150 and the 21150 then has a transaction to initiate on the primary bus, the 21150 starts the transaction if p_gnt_l was asserted during the previous cycle ...
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... The master that initiated the last transaction now has the lowest priority in its group. If the 21150 detects that an initiator has failed to assert s_frame_l after 16 cycles of both grant assertion and a secondary idle bus condition, the arbiter deasserts the grant. That master does not receive any more grants until it deasserts its request for at least one PCI clock cycle ...
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... PCI bus is idle. When p_gnt_l is deasserted, the 21150 tristates the p_ad, p_cbe_l, and p_par signals on the next PCI clock cycle. If the 21150 is parking the primary PCI bus and wants to initiate a transaction on that bus, then the 21150 can start the transaction on the next PCI clock cycle by asserting p_frame_l if p_gnt_l is still asserted ...
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...
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... During secondary interface reset, the gpio interface can be used to shift in a 16-bit serial stream that serves as a secondary bus clock disable mask. • A live insertion bit can be used, along with the gpio<3> pin, to bring the 21150 gracefully to a halt through hardware, permitting live insertion of option cards behind the 21150. 10.1 ...
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... Secondary Clock Control The 21150 uses the gpio pins and the msk_in signal to input a 16-bit serial data stream. This data stream is shifted into the secondary clock control register and is used for selectively disabling secondary clock outputs. The serial data stream is shifted in as soon as p_rst_l is detected deasserted and the secondary reset signal, s_rst_l, is detected asserted ...
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... These bits control the s_clk_o<8:4> outputs: 0 enables the clock, and 1 disables the clock. Bit 13 is the clock enable bit for s_clk_o<9>, which is connected to the 21150’s s_clk input. If desired, the assignment of s_clk_o clock outputs to slots, devices, and the 21150’s s_clk input can be rearranged from the assignment shown here ...
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... Figure 20. Clock Mask Load and Shift Timing After the shift operation is complete, the 21150 tristates the gpio signals and can deassert s_rst_l if the secondary reset bit is clear. The 21150 then ignores msk_in. Control of the gpio signal now reverts to the 21150 gpio control registers ...
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... Once live insertion mode brings the 21150 to a halt and queued transactions are completed, the secondary reset bit in the bridge control register can be used to assert s_rst_l, if desired, to reset and tristate secondary bus devices, and to enable any live insertion hardware. Preliminary Datasheet ...
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...
Page 103
... The 21150 operates at a maximum frequency of 33 MHz MHz if the 21150 is 66 MHz capable. s_clk operates either at the same frequency or at half the frequency as p_clk. ...
Page 104
... After the serial mask has been shifted into the 21150, the value of the mask is readable and modifiable in the secondary clock disable mask register. When the mask is modified by a configuration write operation to this register, the new clock mask disables the appropriate secondary clock outputs within a few cycles ...
Page 105
... The 21150 does not support 33 MHz primary/66 MHz secondary bus operation, where the secondary bus is operating at twice the frequency of the primary bus. If config66 is high and p_m66ena is low (66 MHz capable, primary bus at 33MHz), then the 21150 pulls down s_m66ena to indicate that the secondary bus is operating at 33 MHz. ...
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...
Page 107
... Power has been removed from the 21150. A power-up reset must D3 cold be performed to bring the 21150 to D0. If enabled the bpcce pin, the 21150 will disable the D3 hot secondary clocks and drive them low. Unimplemented power state. The 21150 will ignore the write to the D2 power state bits (power state remains at D0) ...
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Page 109
... All posted write and delayed transaction data buffers are reset; therefore, any transactions residing in 21150 buffers at the time of secondary reset are discarded. When s_rst_l is asserted by means of the secondary reset bit, the 21150 remains accessible during secondary interface reset and continues to respond to accesses to its configuration space from the primary interface ...
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... Chip Reset The chip reset bit in the diagnostic control register can be used to reset the 21150 and the secondary bus. When the chip reset bit is set, all registers and chip state are reset and all signals are tristated.In addition, s_rst_l is asserted, and the secondary reset bit is automatically set. Signal s_rst_l remains asserted until a configuration write operation clears the secondary reset bit and the serial clock mask has been shifted in ...
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... Software changes the configuration register values that affect 21150 behavior only during initialization. Change these values subsequently only when both the primary and secondary PCI buses are idle, and the data buffers are empty; otherwise, the behavior of the 21150 is unpredictable. Figure 22 shows a summary of the configuration space ...
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... Prefetchable Memory Limit Address I/O Limit Address Upper 16 Bits gpio Input Data Reserved Power Management Capabilities** Data * In the 21150-AA only, these registers are R/W: Subsystem ID and Subsystem Vendor ID. ** These are reserved for the 21150-AA. 104 16 15 Device ID Primary Status Primary Command Class Code ...
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... Primary Command Register—Offset 04h This section describes the primary command register. These bits affect the behavior of the 21150 primary interface, except where noted. Some of the bits are repeated in the bridge control register, to act on the secondary interface. This register must be initialized by configuration software. ...
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... When 0—The 21150 does not respond to I/O or memory transactions on the secondary R/W interface and does not initiate I/O or memory transactions on the primary interface. When 1—The 21150 is enabled to operate as an initiator on the primary bus and responds to I/O and memory transactions initiated on the secondary bus. Reset value: 0. ...
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... Primary Status Register—Offset 06h This section describes the primary status register. These bits affect the status of the 21150 primary interface. Bits reflecting the status of the secondary interface are found in the secondary status register. W1TC indicates that writing bit sets that bit to 0. Writing 0 has no effect. ...
Page 116
... Name R/W R Reserved. Returns 0 when read. Enhanced Capabilities Port (ECP) enable. Reads the 21150-AB and later revisions to indicate that the 21150-AB supports an R enhanced capabilities list. The 21150-AA reads show that this capability is not supported. Indicates whether the primary interface is 66- MHz capable ...
Page 117
... Name R/W No programming interfaces have been defined for PCI-to-PCI bridges. R Reads as 0. Name R/W Reads as 04h to indicate that this bridge R device is a PCI-to-PCI bridge. Name R/W Reads as 06h to indicate that this device bridge device. 21150 Description Description Description Description 109 ...
Page 118
... Master latency timer for the primary interface. Indicates the number of PCI clock cycles from the assertion of p_frame_l to the expiration of the timer when the 21150 is acting as a master on the primary interface. All bits are writable, resulting in a granularity of one PCI clock cycle. ...
Page 119
... Reset value: 0. Name R/W Indicates the number of the PCI bus to which the secondary interface is connected. The 21150 uses this register to determine when to respond to and forward Type 1 configuration transactions on the primary interface, and to R/W determine when to convert them to Type 0 or special cycle transactions on the secondary interface ...
Page 120
... Master latency timer for the secondary interface. Indicates the number of PCI clock cycles from the assertion of s_frame_l to the expiration of the timer when the 21150 is acting as a master on the secondary interface. All bits are writable, resulting in a granularity of one PCI clock cycle. ...
Page 121
... Secondary Status Register—Offset 1Eh This section describes the secondary status register. These bits reflect the status of the 21150 secondary interface. W1TC indicates that writing 1 to that bit sets the bit to 0. Writing 0 has no effect. Dword address = 1Ch Byte enable p_cbe_l<3:0> = 00xxb ...
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... Indicates slowest response to a command on the secondary interface. R Reads as 01b to indicate that the 21150 responds no slower than with medium timing. This bit is set to 1 when the 21150 is acting as a target on the secondary bus and returns a R/W1TC target abort to the secondary bus master. Reset value: 0. ...
Page 123
... R/W The low 4 bits of this register are read only and R return 0. Defines the bottom address of an address range used by the 21150 to determine when to forward memory transactions from one interface to the other. The upper 12 bits are writable and correspond to address bits R/W <31:20>. The lower 20 bits of the address are assumed ...
Page 124
... R return 1h to indicate that this range supports 64-bit addressing. Defines the bottom address of an address range used by the 21150 to determine when to forward memory read and write transactions from one interface to the other. The upper 12 bits are writable and correspond to address bits <31:20>. The lower 20 bits of the address R/W are assumed ...
Page 125
... Reset value: 0. Name R/W Defines the upper 16 bits of a 32-bit bottom address of an address range used by the 21150 to determine when to forward I/O transactions from one interface to the other. R/W The I/O address range adheres to 4KB alignment and granularity. Reset value: 0. 21150 ...
Page 126
... Reset to 0. Name R/W Enhanced Capabilities Port (ECP) offset pointer. Reads as DCh in the 21150-AB and later revisions to indicate that the first item, R which corresponds to the power management registers, resides at that configuration offset. This is a R/W register with no side effects in the 21150-AA ...
Page 127
... ID that R/W can be initialized during POST. This register is only implemented in the 21150-AA. Reset to 0. Name R/W Reads indicate that the 21150 does not R have an interrupt pin. Name R/W Controls the 21150’s response when a parity error is detected on the secondary interface. ...
Page 128
... Reserved 120 Name R/W Controls whether the 21150 asserts p_serr_l when it detects s_serr_l asserted. When 0—The 21150 does not drive p_serr_l in response to s_serr_l assertion. R/W When 1—The 21150 asserts p_serr_l when s_serr_l is detected asserted (the primary SERR# driver enable bit must also be set). ...
Page 129
... PCI bus. Reset value: 0. Sets the maximum number of PCI clock cycles that the 21150 waits for an initiator on the primary bus to repeat a delayed transaction request. The counter starts once the delayed transaction completion is at the head of the queue ...
Page 130
... Master timeout status Master timeout SERR# 27 enable 31:28 Reserved 15.1.32 Capability ID Register—Offset DCh This section describes the capability ID register. (Implemented in the 21150-AB and later revisions only. In the 21150-AA, these registers are reserved.) Dword address = DCh Byte enable p_cbe_l<3:0> = xxx0b Dword Bit 7:0 CAP_ID 122 ...
Page 131
... Next Item Ptr Register—Offset DDh This section describes the next item ptr register. (Implemented in the 21150-AB and later revisions only. In the 21150-AA, these registers are reserved.) Dword address = DCh Byte enable p_cbe_l<3:0> = xx0xb Dword Bit 15:8 NEXT_ITEM 15.1.34 Power Management Capabilities Register—Offset DEh This section describes the power management capabilities register ...
Page 132
... DATA_SEL 14:13 DATA_SCALE 15 PME_STAT 15.1.36 PPB Support Extensions Registers—Offset E2h This section describes the PPB support extensions registers. (Implemented in the 21150-AB and later revisions only. In the 21150-AA, these registers are reserved.) Dword address = E0h Byte enable p_cbe_l<3:0> = x0xxb Dword Bit 21:16 Reserved 22 B2_B3 ...
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... Data 15.2 Device-Specific Configuration Registers This section provides a detailed description of the 21150 device-specific configuration registers. Each field has a separate description. Fields that have the same configuration address are selectable by turning on (driving low) the appropriate byte enable bits on p_cbe_l during the data phase. To select all fields of a configuration address, drive all byte enable bits low ...
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... When 1—The 21150 requests only one Dword R/W from the target during memory read transactions and forwards read byte enable bits. The 21150 returns a target disconnect to the requesting master on the first data transfer. Memory read line and memory read multiple transactions are still prefetchable. ...
Page 135
... When 1—Causes the 21150 to perform a chip reset. Data buffers, configuration registers, and both the primary and secondary interfaces are reset to their initial state. The 21150 clears this bit once chip reset is complete. The 21150 can then be R/W1TR reconfigured. Secondary bus reset s_rst_l is asserted and the secondary reset bit in the bridge control register is set when this bit is set ...
Page 136
... When 1—Signal p_serr_l is not asserted if this event occurs. Reset value: 0. Controls the 21150’s ability to assert p_serr_l when it receives a master abort when attempting to deliver posted write data. When 0—Signal p_serr_l is asserted if this event occurs and the SERR# enable bit in the R/W command register is set ...
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... GPIO output write-1-to- 15:12 set Preliminary Datasheet Name R/W Controls the 21150’s ability to assert p_serr_l when it is unable to deliver delayed write data after 2 When 0—Signal p_serr_l is asserted if this event occurs and the SERR# enable bit in the R/W command register is set. When 1—Signal p_serr_l is not asserted if this event occurs ...
Page 138
... Output Enable Control Register—Offset 66h This section describes the gpio output enable control register. Dword address = 64h Byte enable p_cbe_l<3:0> = x0xxb Dword Bit GPIO output enable write- 19:16 1-to-clear GPIO output enable write- 23:20 1-to-set 15.2.7 gpio Input Data Register—Offset 67h This section describes the gpio input data register ...
Page 139
... When 1—Signal s_clk_o<7> is disabled and R/W driven low. Upon secondary bus reset, this bit is initialized by shifting in a serial data stream. When 0—Signal s_clk_o<8> is enabled. When 1—Signal s_clk_o<8> is disabled and R/W driven low. Upon secondary bus reset, this bit is initialized by shifting in a serial data stream. 21150 Description 131 ...
Page 140
... The 21150 clock disable 15:14 Reserved 15.2.9 p_serr_l Status Register—Offset 6Ah This section describes the p_serr_l status register. This status register indicates the reason for the 21150’s assertion of p_serr_l. Dword address = 68h Byte enable p_cbe_l<3:0> = x0xxb Dword Bit 16 Address parity error ...
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... Delayed transaction 23 master timeout 15.3 Configuration Register Values After Reset Table 35 lists the value of the 21150 configuration registers after reset. Reserved registers are not listed and are always read as 0. Table 35. Configuration Register Values After Reset (Sheet Byte Address 00–01h 02–03h 04– ...
Page 142
... Reserved in the 21150-AA. 134 Register Name Prefetchable memory limit Prefetchable memory base upper 32 bits Prefetchable memory limit upper 32 bits I/O base upper 16 bits I/O limit upper 16 bits Subsystem vendor ID–21150-AA only ECP pointer Subsystem ID–21150-AA only Reserved Interrupt pin Bridge control Chip control Diagnostic control ...
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... A test access port controller • An instruction register • A bypass register • A boundary-scan register Note: The JTAG test access port used only while the 21150 is not operating. 16.2 JTAG Signal Pins This chapter describes the JTAG pins listed in Table 36. JTAG Pins Signal Name tdi ...
Page 144
... Instruction Register The 5-bit instruction register selects the test modes and features.The instruction register bits are interpreted as instructions, as shown in of the boundary-scan and bypass registers. Table 37 describes the 21150’s instructions. Table 37. JTAG Instruction Registers Instruction Register Contents 00000 00001 00010 ...
Page 145
... The cell supports sample, shift, drive output, and hold output functions used at all I/O pins. 16.6.2 21150 Boundary-Scan Order Table 38 lists the boundary-scan register order and the group disable controls. The group disable control either enables or tristates its corresponding group of bidirectional drivers. When the value of a group disable control bit is 0, the output driver is enabled ...
Page 146
... Table 38. Boundary-Scan Order (Sheet Pin Signal Name Number 15 s_gnt_l<4> 16 s_gnt_l<5> 17 s_gnt_l<6> 18 s_gnt_l<7> 19 s_gnt_l<8> 21 s_clk 22 s_rst_l 23 s_cfn_l 24 gpio<3> 25 gpio<2> 27 gpio<1> 28 gpio<0> 29 s_clk_o<0> 30 s_clk_o<1> 32 s_clk_o<2> 33 s_clk_o<3> 35 s_clk_o<4> 36 s_clk_o<5> 38 s_clk_o<6> 39 s_clk_o<7> 41 s_clk_o<8> 42 s_clk_o<9> 43 p_rst_l 45 p_clk 46 p_gnt_l 47 p_req_l 49 p_ad<31> 50 p_ad<30> 55 p_ad<29> 57 p_ad<28> 58 p_ad<27> ...
Page 147
... Group Disable Cell — — — — — — — — — 2 — — — — — — 1 — — — — — — — — ...
Page 148
... Table 38. Boundary-Scan Order (Sheet Pin Signal Name Number 119 p_ad<2> 121 p_ad<1> 122 p_ad<0> 125 config66 126 msk_in tdi tdo 137 s_ad<0> 138 s_ad<1> 140 s_ad<2> 141 s_ad<3> 143 s_ad<4> 144 s_ad<5> 146 s_ad<6> 147 s_ad<7> 149 s_cbe_l<0> 150 s_ad< ...
Page 149
... Group Disable Cell — — — — — — — — — — — — — — — — — — 6 — — 141 ...
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... Absolute Maximum Ratings The 21150 is specified to operate at a maximum frequency of 33 MHz MHz if 66 MHz capable junction temperature (T ratings for the 21150. These are stress ratings only; stressing the device beyond the absolute maximum ratings may cause permanent damage. Operating beyond the functional operating range ...
Page 152
... DC Specifications Table 41 defines the dc parameters met by all 21150 signals under the conditions of the functional operating range. Table 41. DC Parameters Symbol V Supply voltage cc Low-level input V il voltage High-level input V ih voltage Low-level V ol output voltage Low-level V ol5V output voltage High-level V oh ...
Page 153
... T high high skew skew T cyc for 3.3-V clocks cc for 3.3-V clocks cc for 3.3-V clocks cc Parameter Minimum Maximum 30 11 — — Table 42 and Figure 24 40. T low low LJ-04738.AI4 Unit V/ 21150 145 ...
Page 154
... Table 42. 33 MHz PCI Clock Signal AC Parameters (Sheet Symbol p_clk falling to T sclkf s_clk_o falling s_clk_0 duty cycle skew T dskew from p_clk duty cycle s_clk_0<x> skew s_clk_0<y> Measured with 30-pF lumped load Table 43. 66 MHz PCI Clock Signal AC Parameters ...
Page 155
... Preliminary Datasheet CLK V test T val Output Valid T on Input Valid T su Note: _ 1.5 V for 5-V signals; 0 test Parameter Minimum Maximum 2 11 1,2 1,2,3 2 — 1,23 — 28 1,2 7 — 1,2,3 10, 12 — 1,2,3 0 — 1,2 21150 T inval T off T h for 3.3-V signals cc LJ-04739.AI4 Unit 147 ...
Page 156
... Table 45. 66 MHz PCI Signal Timing Symbol CLK to signal valid delay— T val bused signals CLK to signal valid delay— T val(ptp) point-to- point Float to active T on delay Active to float T off delay Input setup T time—bused su signals Input setup time to CLK— ...
Page 157
... Datasheet Parameter Minimum Maximum 100 — — 1 show the gpio timing specifications. See also Parameter Minimum Maximum — — — — 0 — — 13.5 30 — — 0 — 21150 Unit s Cycles mV/ns Figure 24. Unit 149 ...
Page 158
... Table 48. 66 MHz gpio Timing Specifications Symbol s_clk-to-gpio T vgpio output valid gpio float-to- T gon active delay gpio active-to- T goff float delay gpio-to-s_clk T gsu setup time gpio hold time T gh after s_clk s_clk-to- gpio<0> shift T gcval clock output valid gpio< ...
Page 159
... T from tck falling jd edge tdo float delay T from tck falling jfd edge 1. Measured between 0.8 V and 2 Measured between 2.0 V and 0 pF. Preliminary Datasheet Parameter Minimum Maximum 25 — — — 30 21150 Unit 151 ...
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Page 161
... Mechanical Specifications The 21150 is contained in an industry-standard 208-pin plastic quad flat pack (PQFP) package, shown in Figure 25. Figure 25. 208-Pin PQFP Package (A) A2 Detail "A" Preliminary Datasheet - Pin 1 208-Pin PQFP See Detail "A" ddd ...
Page 162
... Table 50 lists the 208-pin package dimensions in millimeters. Table 50. 208-Pin PQFP Package Dimensions Symbol LL Lead Length e Lead pitch L Foot length A Package overall height 1 A1 Package standoff height 2 A2 Package thickness b Lead width c Lead thickness ccc Coplanarity ddd Lead skew D Package overall width ...
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