S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 109

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
DDRR
DDRR
DDRR
DDRR
DDRR
Field
3-0
7
6
5
4
Port R data direction—
This register controls the data direction of pin 7.This register configures pin as either input or output.
If LCD segment driver output is enabled, it will force as input/output disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port R data direction—
This register controls the data direction of pin 6.This register configures pin as either input or output.
If LCD segment driver output is enabled, it will force as input/output disabled
Else If IIC is routing to PR and IIC is enabled, it will force as open-drain output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port R data direction—
This register controls the data direction of pin 5.This register configures pin as either input or output.
If LCD segment driver output is enabled, it will force as input/output disabled
Else If IIC is routing to PR and IIC is enabled, it will force as open-drain output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port R data direction—
This register controls the data direction of pin 4.This register configures pin as either input or output.
If LCD segment driver output is enabled, it will force as input/output disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port R data direction—
This register controls the data direction of pin 3-0.This register configures pin as either input or output.
If TIM1/TIM0 are routing to the PR and TIM1/TIM0 output compare functions are enabled, it will force as output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTR or PTIR registers, when changing the
DDRR register.
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Table 2-49. DDRR Register Field Descriptions
NOTE
Description
Port Integration Module (S12HYPIMV1)
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