S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 689

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

to a logic high state. PWM output on M2C1M results in a positive current flow through coil 1 when
M2C1P is driven to a logic high state.
19.2.4
High current PWM output pins that can be used for motor drive. These pins interface to the coils of
motor 3. PWM output on M3C0M results in a positive current flow through coil 0 when M3C0P is driven
to a logic high state. PWM output on M3C1M results in a positive current flow through coil 1 when
M3C1P is driven to a logic high state.
19.3
This section provides a detailed description of all registers of the 10-bit 8-channel motor controller
module.
19.3.1
Figure 19-2
Freescale Semiconductor
Memory Map and Register Definition
0x000A
0x000B
0x000C
0x000D
0x000E
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
0x000F
0x0010
0x0011
0x0012
0x0013
0x0014
0x0015
Offset
M3C0M/M3C0P/M3C1M/M3C1P — PWM Output Pins for Motor 3
Module Memory Map
shows the memory map of the 10-bit 8-channel motor controller module.
Motor Controller Control Register 0 (MCCTL0)
Motor Controller Control Register 1 (MCCTL1)
Motor Controller Period Register (High Byte)
Motor Controller Period Register (Low Byte)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Motor Controller Channel Control Register 0 (MCCC0)
Motor Controller Channel Control Register 1 (MCCC1)
Motor Controller Channel Control Register 2 (MCCC2)
Motor Controller Channel Control Register 3 (MCCC3)
Motor Controller Channel Control Register 4 (MCCC4)
Motor Controller Channel Control Register 5 (MCCC5)
1
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Figure 19-2. MC10B8C Memory Map
Register
Motor Controller (MC10B8CV1)
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
—
—
—
—
—
—
—
—
—
—
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