S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 697

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.4
19.4.1
19.4.1.1
The motor controller is configurable between three output modes.
The mode of operation for each PWM channel is determined by the corresponding MCOM[1:0] bits in
channel control registers. After a reset occurs, each PWM channel will be disabled, the corresponding pins
are released.
Each PWM channel consists of two pins. One output pin will generate a PWM signal. The other will
operate as logic high or low output depending on the state of the RECIRC bit (refer to
“RECIRC
state of the S bit in the duty cycle register determines the pin where the PWM signal is driven in full
H-bridge mode. While in half H-bridge mode, the state of the released pin is determined by other modules
associated with this pin.
Associated with each PWM channel pair n are two PWM channels, x and x + 1, where x = 2 * n and n
(0, 1, 2, 3) is the PWM channel pair number. Duty cycle register x controls the sign of the PWM signal
(which pin drives the PWM signal) and the duty cycle of the PWM signal for motor controller channel x.
The pins associated with PWM channel x are MnC0P and MnC0M. Similarly, duty cycle register x + 1
controls the sign of the PWM signal and the duty cycle of the PWM signal for channel x + 1. The pins
associated with PWM channel x + 1 are MnC1P and MnC1M. This is summarized in
Freescale Semiconductor
•
•
•
Pair Number
Dual full H-bridge mode can be used to control either a stepper motor or a 360 air core instrument.
In this case two PWM channels are combined.
In full H-bridge mode, each PWM channel is updated independently.
In half H-bridge mode, one pin of the PWM channel can generate a PWM signal to control a 90
air core instrument (or other load requiring a PWM signal) and the other pin is unused.
Channel
PWM
Functional Description
Bit”), while in (dual) full H-bridge mode, or will be released, while in half H-bridge mode. The
n
0
Modes of Operation
Table 19-11. Corresponding Registers and Pin Names for Each PWM Channel Pair
PWM Output Modes
Channel Control
MCMCx + 1
Register
MCMCx
MCMC0
MCMC1
PWM
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Duty Cycle
MCDCx + 1
Register
MCDC0
MCDC1
MCDCx
PWM Channel x + 1, x = 2 n
PWM Channel x, x = 2 n
PWM Channel 0
PWM Channel 1
Channel
Number
Motor Controller (MC10B8CV1)
Section 19.4.1.3.3,
Table
MnC0M
MnC1M
M0C0M
M0C1M
Names
MnC0P
MnC1P
M0C0P
M0C1P
19-11.
Pin
697