S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 313

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.3.2
This section describes in detail all the registers and register bits in the MSCAN module. Each description
includes a standard register diagram with an associated figure number. Details of register bit and field
function follow the register diagrams, in bit order. All bits of all registers in this module are completely
synchronous to internal clocks during a register read.
9.3.2.1
The CANCTL0 register provides various control bits of the MSCAN module as described below.
Freescale Semiconductor
Module Base + 0x0000
0x001C–0x001F
0x0018–0x001B
0x0020–0x002F
0x0030–0x003F
0x0010–0x0013
0x0014–0x0017
CANIDMR4–7
CANIDAR0–3
CANIDAR4–7
CANTXERR
CANIDMRx
CANRXFG
CANTXFG
Register
0x000F
Reset:
Name
W
R
Register Descriptions
MSCAN Control Register 0 (CANCTL0)
RXFRM
0
7
R
W
R
W
R
W
R
W
R
W
R
W
R
W
TXERR7
Bit 7
AM7
AM7
AC7
AC7
= Unimplemented
RXACT
Figure 9-3. MSCAN Register Summary (continued)
Figure 9-4. MSCAN Control Register 0 (CANCTL0)
6
0
MC9S12HY/HA-Family Reference Manual Rev. 1.04
= Unimplemented or Reserved
TXERR6
AM6
AM6
AC6
AC6
6
See
See
CSWAI
0
Section 9.3.3, “Programmer’s Model of Message
Section 9.3.3, “Programmer’s Model of Message
5
TXERR5
AM5
AM5
AC5
AC5
5
SYNCH
4
0
TXERR4
AM4
AM4
AC4
AC4
Freescale’s Scalable Controller Area Network (S12MSCANV3)
4
TIME
0
3
TXERR3
AM3
AM3
AC3
AC3
3
WUPE
TXERR2
2
0
AM2
AM2
AC2
AC2
2
Storage”
Storage”
Access: User read/write
SLPRQ
TXERR1
0
1
AM1
AM1
AC1
AC1
1
INITRQ
TXERR0
Bit 0
AM0
AM0
AC0
AC0
0
1
313
(1)