S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 140

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

S12P Memory Map Control (S12PMMCV1)
3.3.2.3
Read: Anytime
Write: Anytime
These four index bits are used to map 16KB blocks into the Flash page window located in the local (CPU
or BDM) memory map from address 0x8000 to address 0xBFFF (see
up to 256 KB of Flash (in the Global map) within the 64KB Local map. The PPAGE index register is
effectively used to construct paged Flash addresses in the Local map format. The CPU has special access
to read and write this register directly during execution of CALL and RTC instructions.
140
Address: 0x0015
Reset
W
R
MOVB
LDY
Example 3-1. This example demonstrates usage of the Direct Addressing Mode
Program Page Index Register (PPAGE)
0
0
7
Writes to this register using the special access of the CALL and RTC
instructions will be complete before the end of the instruction execution.
#0x80,DIRECT
<00
Bit17
0
0
6
PPAGE Register [3:0]
Figure 3-7. Program Page Index Register (PPAGE)
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Figure 3-8. PPAGE Address Mapping
0
0
5
;Set DIRECT register to 0x80. Write once only.
;Global data accesses to the range 0xXX_80XX can be direct.
;Logical data accesses to the range 0x80XX are direct.
;Load the Y index register from 0x8000 (direct access).
;< operator forces direct access on some assemblers but in
;many cases assemblers are “direct page aware” and can
;automatically select direct mode.
Global Address [17:0]
Bit14
NOTE
0
0
4
Bit13
Address: CPU Local Address
PIX3
1
3
Address [13:0]
or BDM Local Address
Figure
PIX2
1
2
3-8). This supports accessing
Bit0
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PIX1
1
1
PIX0
0
0