S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 147

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.5.2
The S12PMMC controls the address buses and the data buses that interface the bus masters (CPU12,
S12SBDM) with the rest of the system (master buses). In addition the MMC handles all CPU read data
bus swapping operations. All internal resources are connected to specific target buses (see
3.5.2.1
The arbitration scheme allows only one master to be connected to a target at any given time. The following
rules apply when prioritizing accesses from different masters to the same target bus:
3.5.3
The MMC does not generate any interrupts
Freescale Semiconductor
•
•
CPU12 always has priority over BDM.
BDM has priority over CPU12 when its access is stalled for more than 128 cycles. In the later case
the CPU will be stalled after finishing the current operation and the BDM will gain access to the
bus.
Chip Bus Control
Interrupts
Master Bus Prioritization regarding Access Conflicts on Target Buses
P-Flash
DBG
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
D-Flash
Figure 3-12. S12P platform
MMC “Crossbar Switch”
resources
CPU
BDM
XBUS0
S12X0
SRAM
S12P Memory Map Control (S12PMMCV1)
S12X1
Peripherals
BDM
IPBI
Figure
3-12).
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