S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 201

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.3.2.8.2
The DBGC1_COMRV bits determine which comparator address registers are visible in the 8-byte window
from 0x0028 to 0x002F as shown in
Read: Anytime. See
Write: If DBG not armed. See
6.3.2.8.3
Read: Anytime. See
Write: If DBG not armed. See
Freescale Semiconductor
Address: 0x0029
Address: 0x002A
Bit[17:16]
Reset
Reset
Field
1–0
W
W
R
R
Bit 15
Comparator Address High Compare Bits — The Comparator address high compare bits control whether the
selected comparator compares the address bus bits [17:16] to a logic one or logic zero.
0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
0
0
0
7
7
Debug Comparator Address High Register (DBGXAH)
Debug Comparator Address Mid Register (DBGXAM)
Figure 6-16. Debug Comparator Address High Register (DBGXAH)
Figure 6-17. Debug Comparator Address Mid Register (DBGXAM)
Table 6-24
Table 6-24
= Unimplemented or Reserved
Bit 14
0
0
0
6
6
Table 6-24. Comparator Address Register Visibility
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Table 6-24
Table 6-24
for visible register encoding.
for visible register encoding.
Table 6-25. DBGXAH Field Descriptions
COMRV
Bit 13
Table 6-24.
00
01
10
11
0
0
0
5
5
for visible register encoding.
for visible register encoding.
DBGCAH, DBGCAM, DBGCAL
DBGAAH, DBGAAM, DBGAAL
DBGBAH, DBGBAM, DBGBAL
Bit 12
Visible Comparator
0
0
0
4
4
Description
None
Bit 11
0
0
0
3
3
Bit 10
0
0
0
2
2
S12S Debug Module (S12SDBGV2)
Bit 17
Bit 9
0
0
1
1
Bit 16
Bit 8
0
0
0
0
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