S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 675

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The voltage levels required for the different operating modes are generated internally based on VLCD.
Changing VLCD alters the differential RMS voltage across the segments in the ON and OFF states,
thereby setting the display contrast.
The backplane waveforms are continuous and repetitive every frame. They are fixed within each operating
mode and are not affected by the data in the LCD RAM.
The frontplane waveforms generated are dependent on the state (ON or OFF) of the LCD segments as
defined in the LCD RAM. The LCD40F4BV1 driver hardware uses the data in the LCD RAM to construct
the frontplane waveform to create a differential RMS voltage necessary to turn the segment ON or OFF.
The LCD duty is decided by the DUTY1 and DUTY0 bits in the LCD control register 0 (LCDCR0). The
number of bias voltage levels is determined by the BIAS bit in LCDCR0.
multiplex modes (duties) and the bias voltage levels that can be selected for each multiplex mode (duty).
The backplane pins have their corresponding backplane waveform output BP[3:0] in high impedance state
when in the OFF state as indicated in
used for other functionality, for example as general purpose I/O ports.
18.4.2
The LCD40F4BV1 driver system operation during wait mode is controlled by the LCD stop in wait
(LCDSWAI) bit in the LCD control register 1 (LCDCR1). If LCDSWAI is reset, the LCD40F4BV1 driver
system continues to operate during wait mode. If LCDSWAI is set, the LCD40F4BV1 driver system is
turned off during wait mode. In this case, the LCD waveform generation clocks are stopped and the
LCD40F4BV1 drivers pull down to VSSX those frontplane and backplane pins that were enabled before
entering wait mode. The contents of the LCD RAM and the LCD registers retain the values they had prior
to entering wait mode.
18.4.3
All LCD40F4BV1 driver system clocks are stopped, the LCD40F4BV1 driver system pulls down to VSSX
those frontplane and backplane pins that were enabled before entering stop mode. Also, during stop mode,
the contents of the LCD RAM and the LCD registers retain the values they had prior to entering stop mode.
As a result, after exiting from stop mode, the LCD40F4BV1 driver system clocks will run (if LCDEN =
1) and the frontplane and backplane pins retain the functionality they had prior to entering stop mode.
Freescale Semiconductor
Duty
1/1
1/2
1/3
1/4
DUTY1
LCDCR0 Register
Operation in Wait Mode
Operation in Stop Mode
0
1
1
0
DUTY0
1
0
1
0
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
BP3
OFF
OFF
OFF
BP3
Table 18-9. LCD Duty and Bias
Table
OFF
OFF
BP2
BP2
BP2
Backplanes
18-9. In the OFF state the corresponding pins BP[3:0]can be
BP1
OFF
BP1
BP1
BP1
BP0
BP0
BP0
BP0
BP0
Liquid Crystal Display (LCD40F4BV1) Block Description
YES
1/1
NA
NA
NA
Bias (BIAS = 0)
YES
1/2
NA
NA
NA
Table 18-9
YES
YES
1/3
NA
NA
YES
summarizes the
1/1
NA
NA
NA
Bias (BIAS = 1)
1/2
NA
NA
NA
NA
YES
YES
YES
1/3
NA
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