S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 696

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Motor Controller (MC10B8CV1)
Whenever FAST = 1, the bits D10, D9, D1, and D0 will be set to 0 if the duty cycle register is written.
For example setting MCDCx = 0x0158 with FAST = 0 gives the same output waveform as setting
MCDCx = 0x5600 with FAST = 1 (with FAST = 1, the low byte of MCDCx needs not to be written).
The state of the FAST bit has impact only during write and read operations. A change of the FAST bit (set
or clear) without writing a new value does not impact the internal interpretation of the duty cycle values.
To prevent the output from inconsistent signals, the duty cycle registers are double buffered. The motor
controller module will use working registers to generate the output signals. The working registers are
copied from the bus accessible registers at the following conditions:
In this way, the output of the PWM will always be either the old PWM waveform or the new PWM
waveform, not some variation in between.
Reads of this register return the most recent value written. Reads do not necessarily return the value of the
currently active sign, duty cycle, and dither functionality due to the double buffering scheme.
1. Odd duty cycle register: MCDCx+1, x = 2 n
696
Offset Module Base + 0x0020 . . . 0x002F
Reset
Field
•
•
•
•
S
0
W
R
MCPER is set to 0 (all channels are disabled in this case)
MCAM[1:0] of the respective channel is set to 0 (channel is disabled)
A PWM timer counter overflow occurs while in half H-bridge or full H-bridge mode
A PWM channel pair is configured to work in Dual Full H-Bridge mode and a PWM timer counter
overflow occurs after the odd
15
S
0
SIGN — The SIGN bit is used to define which output will drive the PWM signal in (dual) full-H-bridge modes. The
= Unimplemented or Reserved
SIGN bit has no effect in half-bridge modes. See
detailed information about the impact of RECIRC and SIGN bit on the PWM output.
Figure 19-9. Motor Controller Duty Cycle Register x (MCDCx) with FAST = 1
D8
14
0
D7
13
0
D6
12
0
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Table 19-10. MCDCx Field Descriptions
D5
11
0
1
duty cycle register of the channel pair has been written.
D4
10
0
D3
9
0
D2
8
0
Description
Section 19.4.1.3.2, “Sign Bit
7
0
0
6
0
0
5
0
0
4
0
0
(S)”, and table
3
0
0
Freescale Semiconductor
Access: User read/write
2
0
0
Table 19-12
1
0
0
0
0
0
for