S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 154

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Interrupt Module (S12SINTV1)
4.4
The INT module processes all exception requests to be serviced by the CPU module. These exceptions
include interrupt vector requests and reset vector requests. Each of these exception types and their overall
priority level is discussed in the subsections below.
4.4.1
The CPU handles both reset requests and interrupt requests. A priority decoder is used to evaluate the
priority of pending interrupt requests.
4.4.2
The INT module contains a priority decoder to determine the priority for all interrupt requests pending for
the CPU. If more than one interrupt request is pending, the interrupt request with the higher vector address
wins the prioritization.
The following conditions must be met for an I bit maskable interrupt request to be processed.
Since an interrupt vector is only supplied at the time when the CPU requests it, it is possible that a higher
priority interrupt request could override the original interrupt request that caused the CPU to request the
vector. In this case, the CPU will receive the highest priority vector and the system will process this
interrupt request first, before the original interrupt request is processed.
154
IVB_ADDR[7:0]
1. The local interrupt enabled bit in the peripheral module must be set.
2. The I bit in the condition code register (CCR) of the CPU must be cleared.
3. There is no SWI, TRAP, or X bit maskable request pending.
Field
7–0
Functional Description
S12S Exception Requests
Interrupt Prioritization
All non I bit maskable interrupt requests always have higher priority than
the I bit maskable interrupt requests. If the X bit in the CCR is cleared, it is
possible to interrupt an I bit maskable interrupt by an X bit maskable
interrupt. It is possible to nest non maskable interrupt requests, e.g., by
nesting SWI or TRAP calls.
Interrupt Vector Base Address Bits — These bits represent the upper byte of all vector addresses. Out of
reset these bits are set to 0xFF (i.e., vectors are located at 0xFF80–0xFFFE) to ensure compatibility to
HCS12.
Note: A system reset will initialize the interrupt vector base register with “0xFF” before it is used to determine
Note: If the BDM is active (i.e., the CPU is in the process of executing BDM firmware code), the contents of
the reset vector address. Therefore, changing the IVBR has no effect on the location of the three reset
vectors (0xFFFA–0xFFFE).
IVBR are ignored and the upper byte of the vector address is fixed as “0xFF”. This is done to enable
handling of all non-maskable interrupts in the BDM firmware.
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Table 4-3. IVBR Field Descriptions
NOTE
Description
Freescale Semiconductor