S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 117

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
1
2.3.74
2.3.75
Freescale Semiconductor
Address 0x0291
Address 0x0292
Read: Anytime.
Write:Never, writes to this register have no effect.
Read: Anytime.
Write: Anytime.
7,5,3,1
6,4,2,0
DDRU
DDRU
Field
Field
PTIU
Reset
Reset
7-0
W
W
R
R
Port U input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
Port U data direction—
If enabled the Motor driver PWM output it will force the I/O state to be output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port U data direction—
If enabled the Motor driver PWM output it will force the I/O state to be output.
Else if corresponding TIM0 output compare channel is enabled, it will be force as output
1 Associated pin is configured as output.
0 Associated pin is configured as input.
DDRU7
PTIU7
Port U Input Register (PTIU)
Port U Data Direction Register (DDRU)
u
0
7
7
= Unimplemented or Reserved
DDRU6
PTIU6
u
0
6
6
Figure 2-73. Port U Data Direction Register (DDRU)
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Table 2-64. DDRU Register Field Descriptions
Table 2-63. PTIU Register Field Descriptions
Figure 2-72. Port U Input Register (PTIU)
DDRU5
PTIU5
u
0
5
5
DDRU4
PTIU4
u
0
4
4
Description
Description
u = Unaffected by reset
DDRU3
PTIU3
3
u
3
0
DDRU2
PTIU2
Port Integration Module (S12HYPIMV1)
u
0
2
2
DDRU1
Access: User read/write
PTIU1
u
0
1
1
Access: User read
DDRU0
PTIU0
u
0
0
0
117
1
1