S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 695

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.3.2.5
Each duty cycle register sets the sign and duty functionality for the respective PWM channel.
The contents of the duty cycle registers define DUTY, the number of motor controller timer counter clocks
the corresponding output is driven low (RECIRC = 0) or is driven high (RECIRC = 1). Setting all bits to 0
will give a static high output in case of RECIRC = 0; otherwise, a static low output. Values greater than
or equal to the contents of the period register will generate a static low output in case of RECIRC = 0, or
a static high output if RECIRC = 1. The layout of the duty cycle registers differ dependent upon the state
of the FAST bit in the control register 0.
Freescale Semiconductor
Offset Module Base + 0x0020 . . . 0x002F
Reset
W
R
15
S
0
Motor Controller Duty Cycle Registers
The PWM motor controller will release the pins after the next PWM timer
counter overflow without accommodating any channel delay if a single
channel has been disabled or if the period register has been cleared or all
channels have been disabled. Program one or more inactive PWM frames
(duty cycle = 0) before writing a configuration that disables a single channel
or the entire PWM motor controller.
= Unimplemented or Reserved
Figure 19-8. Motor Controller Duty Cycle Register x (MCDCx) with FAST = 0
14
S
0
CD[1:0]
13
S
0
00
01
10
11
12
S
0
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
11
S
0
Table 19-9. Channel Delay
D10
10
0
D9
9
0
NOTE
n [# of PWM Clocks]
D8
8
0
0
1
2
3
D7
7
0
D6
6
0
D5
5
0
D4
4
0
Motor Controller (MC10B8CV1)
D3
3
0
Access: User read/write
D2
2
0
D1
1
0
D0
0
0
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