S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 663

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 18
Liquid Crystal Display (LCD40F4BV1) Block Description
Revision History
18.1
The LCD40F4BV1 driver module has 40 frontplane drivers and 4 backplane drivers so that a maximum of
160 LCD segments are controllable. Each segment is controlled by a corresponding bit in the LCD RAM.
Four multiplex modes (1/1, 1/2, 1/3, 1/4 duty), and three bias (1/1, 1/2, 1/3) methods are available. The V
voltage is the lowest level of the output waveform and V
backplane pins can be multiplexed with other port functions.
The LCD40F4BV1 driver system consists of five major sub-modules:
18.1.1
The LCD40F4BV1 includes these distinctive features:
Freescale Semiconductor
Number
Version
01.00
01.08
01.09
•
•
•
•
•
Timing and Control – consists of registers and control logic for frame clock generation, bias
voltage level select, frame duty select, backplane select, and frontplane select/enable to produce
the required frame frequency and voltage waveforms.
LCD RAM – contains the data to be displayed on the LCD. Data can be read from or written to the
display RAM at any time.
Frontplane Drivers – consists of 40 frontplane drivers.
Backplane Drivers – consists of 4 backplane drivers.
Voltage Generator – Based on voltage applied to VLCD, it generates the voltage levels for the
timing and control logic to produce the frontplane and backplane waveforms.
Introduction
27-Mar-08
25-Apr-08
Revision
26-Jul-00
Features
Date
Effective
Date
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Author
Table 18-1. LCD40F4BV1 Revision History
initial LCD module spec
New specification for 9S12HY family based on 9S12H family specification
Update for 9S12HY defining last registers as unimplemented
3
becomes the highest level. All frontplane and
Description of Changes
663
0