S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 728

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Electrical Characteristics
A.2
This section describes the characteristics of the analog-to-digital converter.
A.2.1
The
The following constraints exist to obtain full-scale, full range results:
This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that
it ties to. If the input level goes outside of this range it will effectively be clipped.
1. Full accuracy is not guaranteed when differential voltage is less than 4.50 V
2. When converting in Stop Mode (ICLKSTP=1) an ATD Stop Recovery time tATDSTPRCV is required to switch back to bus clock
3. The minimum time assumes a sample time of 4 ATD clock cycles. The maximum time assumes a sample time of 24 ATD clock
A.2.2
Source resistance, source capacitance and current injection have an influence on the accuracy of the ATD.
A further factor is that PortAD pins that are configured as output drivers switching.
A.2.2.1
PortAD output drivers switching can adversely affect the ATD accuracy whilst converting the analog
voltage on other PortAD pins because the output drivers are supplied from the VDDA/VSSA ATD supply
pins. Although internal design measures are implemented to minimize the affect of output driver noise, it
728
Conditions are shown in
Num C
based ATDCLK when leaving Stop Mode. Do not access ATD registers during this time.
cycles and the discharge feature (SMP_DIS) enabled, which adds 2 ATD clock cycles.
1
2
3
4
5
6
7
Table A-12
D Voltage difference V
D Voltage difference V
C Differential reference voltage
C ATD Clock Frequency (derived from bus clock via the
P ATD Clock Frequency in Stop mode (internal generated
D ADC conversion in stop, recovery time
D
V
SSA
prescaler bus)
temperature and voltage dependent clock, ICLK)
ATD Conversion Period
10 bit resolution:
8 bit resolution:
ATD Characteristics
ATD Operating Characteristics
Factors Influencing Accuracy
Port AD Output Drivers Switching
V
RL
and
Table A-13
Table A-4
V
IN
DDX
SSX
V
(3)
/V
/V
unless otherwise noted, supply voltage 3.13 V < V
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Rating
DDA
SSM
DDM
Table A-12. ATD Operating Characteristics
show conditions under which the ATD operates.
(1)
to V
(V
to V
RH
DDA
SSA
(2)
t
ATDSTPRC
N
V
Symbol
N
f
ATDCLk
RH
CONV10
CONV8
VDDX
VSSX
V
-V
RL
–0.1
–0.1
3.13
0.25
Min
DDA
0.6
19
17
—
< 5.5 V
Typ
5.0
—
0
0
1
Freescale Semiconductor
Max
0.1
0.1
5.5
8.0
1.7
1.5
41
39
Cycles
clock
MHz
MHz
Unit
ATD
us
V
V
V