S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 223

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

S12SDBGV1 SCR encoding because OR possibilities are very limited in the channel encoding. By adding
OR forks as shown in red this scenario is possible.
On simultaneous matches the lowest channel number has priority so with this configuration the forking
from State1 has the peculiar effect that a simultaneous match0/match1 transitions to final state but a
simultaneous match2/match1transitions to state2.
6.5.9
Trigger when a routine/event at M2 follows either M1 or M0.
Trigger when an event M2 is followed by either event M0 or event M1
Scenario 8a and 8b are possible with the S12SDBGV1 and S12SDBGV2 SCR encoding
Freescale Semiconductor
SCR1=1101
SCR1=0111
SCR1=0010
State1
State1
State1
Scenario 8
M1
M01
M2
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
SCR2=1100
SCR2=0101
SCR2=0111
State2
State2
State2
M0
Figure 6-38. Scenario 8b
Figure 6-37. Scenario 8a
Figure 6-36. Scenario 7
M2
M2
M01
M02
Final State
Final State
SCR3=1101
State3
M01
M12
Final State
S12S Debug Module (S12SDBGV2)
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