S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 125

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
2.3.84
Freescale Semiconductor
Address 0x029B
Read: Always reads 0x00
Write: Unimplemented
DDRV
DDRV
Field
Reset
1
0
W
R
Port V data direction—
If enabled the Motor driver PWM output it will force the I/O state to be output
Else if SPI is routing to PV and SPI is enabled, SPI will determined the I/O state
Else if PWM5 is routing to PV, it will force I/O state to be output
Else if SPI is routing to PV and SPI is enabled, SPI will determined the I/O state.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port V data direction—
If enabled the Motor driver PWM output it will force the I/O state to be output
Else if corresponding TIM1 output compare channel is enabled, it will be forced as output
Else if IIC is routing to PV and IIC is enabled, it will force the I/O state to be open drain output, also the input buffer
is enabled
Else if PWM4 is routing to PV, it will force I/O state to be output
Else if SPI is routing to PV and SPI is enabled, SPI will determine the I/O state.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
PIM Reserved Registers
0
0
7
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTV or PTIV registers, when changing the
DDRV register.
= Unimplemented or Reserved
Table 2-70. DDRV Register Field Descriptions (continued)
0
0
6
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Figure 2-82. PIM Reserved Registers
0
0
5
NOTE
0
0
4
Description
u = Unaffected by reset
3
0
0
Port Integration Module (S12HYPIMV1)
0
0
2
0
0
1
Access: User read
0
0
0
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