S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 527

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

All assigned bits in the FERCNFG register are readable and writable.
15.3.2.7
The FSTAT register reports the operational status of the Flash module.
1
CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable
but not writable, while remaining bits read 0 and are not writable.
Freescale Semiconductor
Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see
Offset Module Base + 0x0005
Offset Module Base + 0x0006
Reset
DFDIE
Reset
SFDIE
Field
1
0
W
W
R
R
CCIF
Double Bit Fault Detect Interrupt Enable — The DFDIE bit controls interrupt generation when a double bit fault
is detected during a Flash block read operation.
0 DFDIF interrupt disabled
1 An interrupt will be requested whenever the DFDIF flag is set (see
Single Bit Fault Detect Interrupt Enable — The SFDIE bit controls interrupt generation when a single bit fault
is detected during a Flash block read operation.
0 SFDIF interrupt disabled whenever the SFDIF flag is set (see
1 An interrupt will be requested whenever the SFDIF flag is set (see
Flash Status Register (FSTAT)
0
0
1
7
7
= Unimplemented or Reserved
= Unimplemented or Reserved
Figure 15-10. Flash Error Configuration Register (FERCNFG)
0
0
0
0
6
6
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Figure 15-11. Flash Status Register (FSTAT)
Table 15-13. FERCNFG Field Descriptions
ACCERR
0
0
0
5
5
FPVIOL
0
0
0
4
4
Description
MGBUSY
0
0
0
3
3
Section
Section
Section
32 KByte Flash Module (S12FTMRC32K1V1)
RSVD
15.3.2.8)
0
0
0
2
2
15.3.2.8)
15.3.2.8)
DFDIE
0
0
1
1
1
MGSTAT[1:0]
Section
SFDIE
0
0
0
0
1
15.6).
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