S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 46

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Overview MC9S12HY/HA-Family
1.9
The MCU can operate in different modes. These are described in
The MCU can operate in different power modes to facilitate power saving when full system performance
is not required. These are described in
Some modules feature a software programmable option to freeze the module status whilst the background
debug module is active to facilitate debugging.
1.9.1
The different modes and the security state of the MCU affect the debug features (enabled or disabled). The
operating mode out of reset is determined by the state of the MODC signal during reset (see
The MODC bit in the MODE register shows the current operating mode and provides limited mode
switching during operation. The state of the MODC signal is latched into this bit on the rising edge of
RESET.
1.9.1.1
This mode is intended for normal device operation. The opcode from the on-chip memory is being
executed after reset (requires the reset vector to be programmed correctly). The processor program is
executed from internal memory.
1.9.1.2
This mode is used for debugging single-chip operation, boot-strapping, or security related operations. The
background debug module BDM is active in this mode. The CPU executes a monitor program located in
an on-chip ROM. BDM firmware waits for additional serial commands through the BKGD pin.
1.9.2
The MC9S12HY/HA has two static low-power modes Pseudo Stop and Stop Mode. For a detailed
description refer to S12CPMU section.
1.10
The MCU security mechanism prevents unauthorized access to the Flash memory. Refer to Section 5.4.1
Security and Section 17.5 Security
46
Modes of Operation
Security
Chip Configuration Summary
Low Power Operation
Normal Single-Chip Mode
Special Single-Chip Mode
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Normal single chip
Special single chip
1.9.2 Low Power
Table 1-10. Chip Modes
Chip Modes
Operation.
MODC
1
0
1.9.1 Chip Configuration
Freescale Semiconductor
Summary.
Table
1-10).