S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 406

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pulse-Width Modulator (S12PWM8B8CV1)
Write: Anytime
11.3.2.15 PWM Shutdown Register (PWMSDN)
The PWMSDN register provides for the shutdown functionality of the PWM module in the emergency
cases. For proper operation, channel 7 must be driven to the active level for a minimum of two bus clocks.
Read: Anytime
Write: Anytime
406
Module Base + 0x0024
PWMRSTRT
PWM7ENA
PWM7INL
PWMLVL
PWM7IN
PWMIE
Reset
PWMIF
Field
7
6
5
4
2
1
0
W
R
PWMIF
PWM Interrupt Flag — Any change from passive to asserted (active) state or from active to passive state will
be flagged by setting the PWMIF flag = 1. The flag is cleared by writing a logic 1 to it. Writing a 0 has no effect.
0 No change on PWM7IN input.
1 Change on PWM7IN input
PWM Interrupt Enable — If interrupt is enabled an interrupt to the CPU is asserted.
0 PWM interrupt is disabled.
1 PWM interrupt is enabled.
PWM Restart — The PWM can only be restarted if the PWM channel input 7 is de-asserted. After writing a logic
1 to the PWMRSTRT bit (trigger event) the PWM channels start running after the corresponding counter passes
next “counter == 0” phase. Also, if the PWM7ENA bit is reset to 0, the PWM do not start before the counter
passes $00. The bit is always read as “0”.
PWM Shutdown Output Level If active level as defined by the PWM7IN input, gets asserted all enabled PWM
channels are immediately driven to the level defined by PWMLVL.
0 PWM outputs are forced to 0
1 Outputs are forced to 1.
PWM Channel 7 Input Status — This reflects the current status of the PWM7 pin.
PWM Shutdown Active Input Level for Channel 7 — If the emergency shutdown feature is enabled
(PWM7ENA = 1), this bit determines the active level of the PWM7channel.
0 Active level is low
1 Active level is high
PWM Emergency Shutdown Enable — If this bit is logic 1, the pin associated with channel 7 is forced to input
and the emergency shutdown feature is enabled. All the other bits in this register are meaningful only if
PWM7ENA = 1.
0 PWM emergency feature disabled.
1 PWM emergency feature is enabled.
0
7
= Unimplemented or Reserved
PWMIE
0
6
Figure 11-17. PWM Shutdown Register (PWMSDN)
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Table 11-9. PWMSDN Field Descriptions
PWMRSTRT
0
0
5
PWMLVL
0
4
Description
0
0
3
PWM7IN
0
2
PWM7INL
Freescale Semiconductor
0
1
PWM7ENA
0
0