S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 77

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
2.3.10
2.3.11
Freescale Semiconductor
Address 0x001D (PRR)
Read: Anytime
Write: Anytime
Reset:
Address 0x001C (PRR)
NECLK
DIV16
Field
EDIV
Reset
4-0
7
5
W
R
W
R
No ECLK—Disable ECLK output
This bit controls the availability of a free-running clock on the ECLK pin. This clock has a fixed rate of equivalent to
the internal bus clock.
1 ECLK disabled
0 ECLK enabled
Free-running ECLK predivider—Divide by 16
This bit enables a divide-by-16 stage on the selected EDIV rate.
1 Divider enabled: ECLK rate = EDIV rate divided by 16
0 Divider disabled: ECLK rate = EDIV rate
Free-running ECLK Divider—Configure ECLK rate
These bits determine the rate of the free-running clock on the ECLK pin.
00000 ECLK rate = bus clock rate
00001 ECLK rate = bus clock rate divided by 2
00010 ECLK rate = bus clock rate divided by 3,...
11111 ECLK rate = bus clock rate divided by 32
NECLK
ECLK Control Register (ECLKCTL)
PIM Reserved Register
0
0
7
1
7
= Unimplemented or Reserved
= Unimplemented or Reserved
0
0
6
0
0
6
Table 2-10. ECLKCTL Register Field Descriptions
Figure 2-8. ECLK Control Register (ECLKCTL)
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Figure 2-9. PIM Reserved Register
DIV16
0
0
5
0
5
EDIV4
0
0
4
0
4
Description
EDIV3
3
0
0
3
0
EDIV2
Port Integration Module (S12HYPIMV1)
0
0
2
0
2
Access: User read/write
EDIV1
0
0
1
0
1
Access: User read
EDIV0
0
0
0
0
0
77
1
1