S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 226

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
The Voltage Regulator (IVREG) has the following features:
The Phase Locked Loop (PLL) has the following features:
The Internal Reference Clock (IRC1M) has the following features:
Other features of the S12CPMU include
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Supports crystals or resonators from 4MHz to 16MHz.
High noise immunity due to input hysteresis and spike filtering.
Low RF emissions with peak-to-peak swing limited dynamically
Transconductance (gm) sized for optimum start-up margin for typical crystals
Dynamic gain control eliminates the need for external current limiting resistor
Integrated resistor eliminates the need for external bias resistor.
Low power consumption: Operates from internal 1.8V (nominal) supply, Amplitude control limits
power
Input voltage range from 3.13V to 5.5V
Low-voltage detect (LVD) with low-voltage interrupt (LVI)
Power-on reset (POR)
Low-voltage reset (LVR)
highly accurate and phase locked frequency multiplier
Configurable internal filter for best stability and lock time.
Frequency modulation for defined jitter and reduced emission
Automatic frequency lock detector
Interrupt request on entry or exit from locked condition
Reference clock either external (crystal) or internal square wave (1MHz IRC1M) based.
PLL stability is sufficient for LIN communication, even if using IRC1M as reference clock
Trimmable in frequency
Factory trimmed value for 1MHz in Flash Memory, can be overwritten by application if required
Clock monitor to detect loss of crystal
Autonomous periodical interrupt (API)
Bus Clock Generator
— Clock switch to select either PLLCLK or external crystal/resonator based Bus Clock
— PLLCLK divider to adjust system speed
System Reset generation from the following possible sources:
— Power-on reset (POR)
— Low-voltage reset (LVR)
— Illegal address access
— COP time out
— Loss of oscillation (clock monitor fail)
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Freescale Semiconductor