S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 335

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Read:
Write:
Reset: Undefined because of RAM-based implementation
9.3.3.1
The identifier registers for an extended format identifier consist of a total of 32 bits; ID[28:0], SRR, IDE,
and RTR bits. The identifier registers for a standard format identifier consist of a total of 13 bits; ID[10:0],
RTR, and IDE bits.
Freescale Semiconductor
Register
Register
0x00X0
0x00X1
0x00X2
0x00X3
•
•
•
•
Name
Name
IDR0
IDR1
IDR2
IDR3
For transmit buffers, anytime when TXEx flag is set (see
Flag Register
Section 9.3.2.11, “MSCAN Transmit Buffer Selection Register
For receive buffers, only when RXF flag is set (see
Register
For transmit buffers, anytime when TXEx flag is set (see
Flag Register
Section 9.3.2.11, “MSCAN Transmit Buffer Selection Register
Unimplemented for receive buffers.
Figure 9-24. Receive/Transmit Message Buffer — Extended Identifier Mapping (continued)
Identifier Registers (IDR0–IDR3)
W
W
W
W
Figure 9-25. Receive/Transmit Message Buffer — Standard Identifier Mapping
R
R
R
R
(CANRFLG)”).
Bit 7
Bit 7
ID10
ID2
(CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see
(CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see
= Unused, always read ‘x’
= Unused, always read ‘x’
MC9S12HY/HA-Family Reference Manual Rev. 1.04
ID9
ID1
6
6
ID8
ID0
5
5
RTR
ID7
4
4
Freescale’s Scalable Controller Area Network (S12MSCANV3)
Section 9.3.2.5, “MSCAN Receiver Flag
IDE (=0)
Section 9.3.2.7, “MSCAN Transmitter
Section 9.3.2.7, “MSCAN Transmitter
ID6
3
3
(CANTBSEL)”).
(CANTBSEL)”).
ID5
2
2
ID4
1
1
Bit 0
Bit0
ID3
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