S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 499

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Read: Anytime
Write: Anytime.
14.3.2.10 Timer Interrupt Enable Register (TIE)
Read: Anytime
Write: Anytime.
Freescale Semiconductor
Module Base + 0x000C
EDGnB
EDGnA
C7I:C0I
Reset
Field
Field
7:0
7:0
W
R
Input Capture Edge Control — These eight pairs of control bits configure the input capture edge detector
circuits.
Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in
the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set,
the corresponding flag is enabled to cause a interrupt.
C7I
0
7
C6I
0
6
EDGnB
Figure 14-18. Timer Interrupt Enable Register (TIE)
Table 14-12. Edge Detector Circuit Configuration
0
0
1
1
MC9S12HY/HA-Family Reference Manual Rev. 1.04
Table 14-11. TCTL3/TCTL4 Field Descriptions
Table 14-13. TIE Field Descriptions
C5I
EDGnA
0
5
0
1
0
1
Capture on any edge (rising or falling)
C4I
0
4
Capture on falling edges only
Capture on rising edges only
Description
Description
Capture disabled
Configuration
C3I
0
3
Timer Module (TIM16B8CV2) Block Description
C2I
0
2
C1I
0
1
C0I
0
0
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