S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 694

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Motor Controller (MC10B8CV1)
19.3.2.4
Each PWM channel has one associated control register to control output delay, PWM alignment, and
output mode. The registers are named MCCC0... MCCC7. In the following, MCCC0 is described as a
reference for all eight registers.
694
MCOM[1:0]
MCAM[1:0]
Offset Module Base + 0x0010 . . . 0x0017
Reset
CD[1:0]
Field
7:6
5:4
1:0
W
R
MCOM1
Output Mode — MCOM1, MCOM0 control the PWM channel’s output mode. See
PWM Channel Delay — Each PWM channel can be individually delayed by a programmable number of PWM
PWM Channel Alignment Mode — MCAM1, MCAM0 control the PWM channel’s PWM alignment mode and
Motor Controller Channel Control Registers
7
0
Figure 19-7. Motor Controller Control Register Channel 0–7 (MCCC0–MCCC7)
operation. See
MCAM[1:0] and MCOM[1:0] are double buffered. The values used for the generation of the output waveform
will be copied to the working registers either at once (if all PWM channels are disabled or MCPER is set to 0)
or if a timer counter overflow occurs. Reads of the register return the most recent written value, which are not
necessarily the currently active values.
timer counter clocks. The delay will be n/f
MCOM[1:0]
MCAM[1:0]
= Unimplemented or Reserved
MCOM0
00
01
10
11
00
01
10
11
6
0
Table
Table 19-6. MCCC0–MCCC7 Field Descriptions
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
19-8.
Half H-bridge mode, PWM on MnCxM, MnCxP is released
Half H-bridge mode, PWM on MnCxP, MnCxM is released
MCAM1
Table 19-8. PWM Alignment Mode
5
0
Table 19-7. Output Mode
MCAM0
Dual full H-bridge mode
PWM Alignment Mode
TC
4
0
Full H-bridge mode
. See
Channel disabled
Center aligned
Output Mode
Right aligned
Description
Left aligned
Table
19-9.
3
0
0
2
0
0
Table
Freescale Semiconductor
CD1
19-7.
1
0
CD0
0
0