S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 233

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Addres
0x003A
0x003B
0x003C CPMUCOP
0x003D
0x003E
0x0034
0x0035
0x0036
0x0037
0x0038
0x0039 CPMUCLKS
0x003F
0x02F0
0x02F1
0x02F2
7.3
This section provides a detailed description of all registers accessible in the S12CPMU.
7.3.1
The S12CPMU registers are shown in
Freescale Semiconductor
s
CPMUTEST0
CPMUTEST1
RESERVED
RESERVED
CPMUFLG
CPMUPLL
CPMUINT
CPMURTI
POSTDIV
ARMCOP
REFDIV
APICTL
HTCTL
Memory Map and Registers
LVCTL
CPMU
CPMU
CPMU
CPMU
CPMU
CPMU
CPMU
Name
SYNR
Module Memory Map
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
PLLSEL
APICLK
RTDEC
WCOP
RTIE
Bit 7
RTIF
Bit 7
VCOFRQ[1:0]
REFFRQ[1:0]
0
0
0
0
0
0
0
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
= Unimplemented or Reserved
Figure 7-3. CPMU Register Summary
RSBCK
PORF
PSTP
RTR6
Bit 6
6
0
0
0
0
0
0
0
0
0
Figure
WRTMASK
S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
7-3.
RTR5
VSEL
LVRF
FM1
Bit 5
5
0
0
0
0
0
0
0
0
0
0
LOCKIF
LOCKIE
APIES
RTR4
FM0
Bit 4
4
0
0
0
0
0
0
0
0
APIEA
LOCK
RTR3
PRE
Bit 3
HTE
3
0
0
0
0
0
0
0
SYNDIV[5:0]
POSTDIV[4:0]
APIFE
HTDS
RTR2
LVDS
ILAF
PCE
CR2
Bit 2
2
0
0
0
0
0
REFDIV[3:0]
OSCSEL
OSCIE
OSCIF
RTR1
HTIE
APIE
LVIE
CR1
Bit 1
RTI
1
0
0
0
0
OSCSEL
UPOSC
RTR0
Bit 0
COP
HTIF
APIF
CR0
Bit 0
LVIF
0
0
0
0
0
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