S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 323

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime
9.3.2.8
This register contains the interrupt enable bits for the transmit buffer empty interrupt flags.
Freescale Semiconductor
Module Base + 0x0006
Module Base + 0x0007
Write: Anytime when not in initialization mode; write of 1 clears flag, write of 0 is ignored
TXE[2:0]
Field
2-0
Reset:
Reset:
W
W
R
R
Transmitter Buffer Empty — This flag indicates that the associated transmit message buffer is empty, and thus
not scheduled for transmission. The CPU must clear the flag after a message is set up in the transmit buffer and
is due for transmission. The MSCAN sets the flag after the message is sent successfully. The flag is also set by
the MSCAN when the transmission request is successfully aborted due to a pending abort request (see
Section 9.3.2.9, “MSCAN Transmitter Message Abort Request Register
interrupt is pending while this flag is set.
Clearing a TXEx flag also clears the corresponding ABTAKx (see
Message Abort Acknowledge Register
is cleared (see
When listen-mode is active (see
cannot be cleared and no transmission is started.
Read and write accesses to the transmit buffer will be blocked, if the corresponding TXEx bit is cleared
(TXEx = 0) and the buffer is scheduled for transmission.
0 The associated message buffer is full (loaded with a message due for transmission)
1 The associated message buffer is empty (not scheduled)
MSCAN Transmitter Interrupt Enable Register (CANTIER)
The CANTFLG register is held in the reset state when the initialization
mode is active (INITRQ = 1 and INITAK = 1). This register is writable when
not in initialization mode (INITRQ = 0 and INITAK = 0).
0
0
0
0
7
7
Figure 9-11. MSCAN Transmitter Interrupt Enable Register (CANTIER)
Figure 9-10. MSCAN Transmitter Flag Register (CANTFLG)
Section 9.3.2.9, “MSCAN Transmitter Message Abort Request Register
= Unimplemented
= Unimplemented
Table 9-13. CANTFLG Register Field Descriptions
6
0
0
6
0
0
MC9S12HY/HA-Family Reference Manual Rev. 1.04
Section 9.3.2.2, “MSCAN Control Register 1
0
0
0
0
5
5
(CANTAAK)”). When a TXEx flag is set, the corresponding ABTRQx bit
NOTE
4
0
0
4
0
0
Description
Freescale’s Scalable Controller Area Network (S12MSCANV3)
0
0
0
0
3
3
Section 9.3.2.10, “MSCAN Transmitter
(CANTARQ)”). If not masked, a transmit
TXEIE2
TXE2
2
1
2
0
(CANCTL1)”) the TXEx flags
Access: User read/write
Access: User read/write
TXEIE1
(CANTARQ)”).
TXE1
1
0
1
1
TXEIE0
TXE0
0
1
0
0
323
(1)
(1)