S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 164

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Background Debug Module (S12SBDMV1)
5.3.2.1
Register Global Address 0x3_FF01
1
2
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured, but subject to the following:
164
Special Single-Chip Mode
ENBDM is read as 1 by a debugging environment in special single chip mode when the device is not secured or secured but
fully erased (Flash). This is because the ENBDM bit is set by the standard firmware before a BDM command can be fully
transmitted and executed.
UNSEC is read as 1 by a debugging environment in special single chip mode when the device is secured and fully erased,
else it is 0 and can only be read if not secure (see also bit description).
BDMACT
ENBDM
Field
7
6
— ENBDM should only be set via a BDM hardware command if the BDM firmware commands
— BDMACT can only be set by BDM hardware upon entry into BDM. It can only be cleared by
— All other bits, while writable via BDM hardware or standard BDM firmware write commands,
All Other Modes
are needed. (This does not apply in special single chip mode).
the standard BDM firmware lookup table upon exit from BDM active mode.
should only be altered by the BDM hardware or standard firmware lookup table as part of BDM
command execution.
Enable BDM — This bit controls whether the BDM is enabled or disabled. When enabled, BDM can be made
active to allow firmware commands to be executed. When disabled, BDM cannot be made active but BDM
hardware commands are still allowed.
0 BDM disabled
1 BDM enabled
Note: ENBDM is set by the firmware out of reset in special single chip mode. In special single chip mode with
BDM Active Status — This bit becomes set upon entering BDM. The standard BDM firmware lookup table is
then enabled and put into the memory map. BDMACT is cleared by a carefully timed store instruction in the
standard BDM firmware as part of the exit sequence to return to user code and remove the BDM memory from
the map.
0 BDM not active
1 BDM active
BDM Status Register (BDMSTS)
Reset
the device secured, this bit will not be set by the firmware until after the Flash erase verify tests are
complete.
W
R
ENBDM
0
0
0
7
1
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Figure 5-3. BDM Status Register (BDMSTS)
Table 5-2. BDMSTS Field Descriptions
= Unimplemented, Reserved
= Always read zero
BDMACT
1
0
6
0
0
0
5
Description
SDV
0
0
4
TRACE
0
0
3
= Implemented (do not alter)
0
0
0
2
Freescale Semiconductor
UNSEC
0
0
1
2
0
0
0
0