S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 285

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.2
This section lists all inputs to the ADC12B8C block.
8.2.1
8.2.1.1
This pin serves as the analog input Channel x. It can also be configured as digital port or external trigger
for the ATD conversion.
8.2.1.2
These inputs can be configured to serve as an external trigger for the ATD conversion.
Refer to device specification for availability and connection of these inputs!
8.2.1.3
V
8.2.1.4
These pins are the power supplies for the analog circuitry of the ADC12B8C block.
8.3
This section provides a detailed description of all registers accessible in the ADC12B8C.
8.3.1
Figure 8-2
Freescale Semiconductor
Address
0x0000
0x0001
0x0002
RH
is the high reference voltage, V
Signal Description
Memory Map and Register Definition
ATDCTL0
ATDCTL1
ATDCTL2
gives an overview on all ADC12B8C registers.
Detailed Signal Descriptions
Module Memory Map
Name
ANx (x = 7, 6, 5, 4, 3, 2, 1, 0)
ETRIG3, ETRIG2, ETRIG1, ETRIG0
V
V
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
RH
DDA
, V
, V
W
W
W
RL
R
R
R
SSA
ETRIGSEL
Reserved
Figure 8-2. ADC12B8C Register Summary (Sheet 1 of 2)
Bit 7
0
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
= Unimplemented or Reserved
SRES1
RL
AFFC
6
0
is the low reference voltage for ATD conversion.
ICLKSTP ETRIGLE
SRES0
5
0
NOTE
SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0
Analog-to-Digital Converter (ADC12B8CV1) Block Description
4
0
ETRIGP
WRAP3
3
ETRIGE
WRAP2
2
WRAP1
ASCIE
1
ACMPIE
WRAP0
Bit 0
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