S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 399

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.3.2.5
The PWMCAE register contains eight control bits for the selection of center aligned outputs or left aligned
outputs for each PWM channel. If the CAEx bit is set to a one, the corresponding PWM output will be
center aligned. If the CAEx bit is cleared, the corresponding PWM output will be left aligned. See
Section 11.4.2.5, “Left Aligned Outputs”
detailed description of the PWM output modes.
Read: Anytime
Write: Anytime
11.3.2.6
The PWMCTL register provides for various control of the PWM module.
Read: Anytime
Write: Anytime
There are three control bits for concatenation, each of which is used to concatenate a pair of PWM
channels into one 16-bit channel. When channels 6 and 7are concatenated, channel 6 registers become the
high order bytes of the double byte channel. When channels 4 and 5 are concatenated, channel 4 registers
become the high order bytes of the double byte channel. When channels 2 and 3 are concatenated, channel
Freescale Semiconductor
Module Base + 0x0004
Module Base + 0x0005
CAE[7:0]
Reset
Reset
Field
7–0
W
W
R
R
CON67
CAE7
Center Aligned Output Modes on Channels 7–0
0 Channels 7–0 operate in left aligned output mode.
1 Channels 7–0 operate in center aligned output mode.
PWM Center Align Enable Register (PWMCAE)
PWM Control Register (PWMCTL)
0
0
7
7
Write these bits only when the corresponding channel is disabled.
= Unimplemented or Reserved
CON45
Figure 11-7. PWM Center Align Enable Register (PWMCAE)
CAE6
0
0
6
6
Figure 11-8. PWM Control Register (PWMCTL)
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Table 11-7. PWMCAE Field Descriptions
CON23
CAE5
0
0
5
5
and
Section 11.4.2.6, “Center Aligned Outputs”
CON01
CAE4
NOTE
0
0
4
4
Description
PSWAI
CAE3
0
0
3
3
Pulse-Width Modulator (S12PWM8B8CV1)
CAE2
PFRZ
0
0
2
2
CAE1
0
0
0
1
1
for a more
CAE0
0
0
0
0
0
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