S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 69

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.3.2
The following table summarizes the effect of the various configuration bits, i.e. data direction (DDR),
output level (IO), reduced drive (RDR), pull enable (PE), pull select (PS) on the pin function and pull
device activity.
The configuration bit PS is used for two purposes:
Freescale Semiconductor
Reserved
Reserved
Reserved
Register
0x0294D
0x029C
0x029A
0x029B
0x029E
0x029F
0x0297
0x0298
0x0299
DDRV
Name
PERV
PPSV
SRRV
PTIV
PTV
1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled.
2. Select either a pull-up or pull-down device if PE is active.
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
Register Descriptions
DDRV7
SRRV7
PERV7
PPSV7
PTIV7
PTV7
Bit 7
0
0
0
= Unimplemented or Reserved
DDRV6
SRRV6
PERV6
PPSV6
PTIV6
PTV6
6
0
0
0
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
DDRV5
PERV5
SRRV5
PPSV5
PTIV5
PTV5
5
0
0
0
DDRV4
PERV4
PPSV4
SRRV4
PTIV4
PTV4
4
0
0
0
DDRV3
PERV3
PPSV3
SRRV3
PTIV3
PTV3
3
0
0
0
DDRV2
PERV2
PPSV2
SRRV2
PTIV2
PTV2
Port Integration Module (S12HYPIMV1)
2
0
0
0
DDRV1
SRRV1
PERV1
PPSV1
PTIV1
PTV1
1
0
0
0
DDRV0
SRRV0
PERV0
PPSV0
PTIV0
PTV0
Bit 0
0
0
0
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