S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 54

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Port Integration Module (S12HYPIMV1)
Most I/O pins can be configured by register bits to select data direction and drive strength, to enable and
select pull-up or pull-down devices. Port U/V have register bits to select the slew rate control.
2.1.2
The Port Integration Module includes these distinctive registers:
A standard port pin has the following minimum features:
Optional features supported on dedicated pins:
2.2
This section lists and describes the signals that do connect off-chip.
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Open drain for wired-or connections
Interrupt inputs with glitch filtering
The output slew rate control
Data registers and data direction registers for Ports A, B, H, T, S, P, R, U, V and AD when used as
general purpose I/O
Control registers to enable/disable pull devices and select pull-ups/pull-downs on Ports H, T, S, P,
R, U and V on per-pin basis
Control registers to enable/disable pull-up devices on Port AD on per-pin basis
Single control register to enable/disable pull-down on Ports A and B, on per-port basis and
Single control register to enable/disable pull-up on BKGD pin
Control registers to enable/disable reduced output drive on Ports H, T, S, P, R, U, V and AD on
per-pin basis
Single control register to enable/disable reduced output drive on Ports A and B on per-port basis
Control registers to enable/disable open-drain (wired-or) mode on Ports H, R and S. Control
register to enable/disable slew rate control on Port U and Port V
Interrupt flag register for pin interrupts on Ports R, Port S, Port T and AD
Control register to configure IRQ/XIRQ pin operation
Routing register to support module port relocation
Free-running clock outputs
Input/output selection
5V output drive with two selectable drive strengths
5V digital and analog input
Input with selectable pull-up or pull-down device
External Signal Description
Features
This document assumes the availability of all features (100-pin package
option). Some functions are not available on lower pin count package
options. Refer to the pin-out summary section.
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
NOTE
Freescale Semiconductor