S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 380

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

S
11110+ADR10+ADR9
Slave Add1st 7bits
Inter-Integrated Circuit (IICV3) Block Description
10.4.1.8
The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold
the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces
the master clock into wait states until the slave releases the SCL line.
10.4.1.9
The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After
the master has driven SCL low the slave can drive SCL low for the required period and then release it.If
the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low
period is stretched.
10.4.1.10 Ten-bit Address
A ten-bit address is indicated if the first 5 bits of the first address byte are 0x11110. The following rules
apply to the first address byte.
The address type is identified by ADTYPE. When ADTYPE is 0, 7-bit address is applied. Reversely, the
address is 10-bit address.Generally, there are two cases of 10-bit address.See the Fig.1-14 and 1-15.
In the figure 1-15,the first two bytes are the similar to figure1-14.After the repeated START(Sr),the first
slave address is transmitted again, but the R/W is 1, meaning that the slave is acted as a transmitter.
380
Figure 10-15. A master-receiver addresses a slave-transmitter with a 10-bit address.
Figure 10-14. A master-transmitter addresses a slave-receiver with a 10-bit address
S
Handshaking
Clock Stretching
11110+ADR10+ADR9
Slave Add1st 7bits
ADDRESS
11111XX
11110XX
0000000
0000010
0000011
SLAVE
R/W
0
Figure 10-13.
A1
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Slave Add 2nd byte
R/W
Definition of bits in the first byte
ADR[8:1]
0
R/W BIT
0
x
x
x
x
A1
Slave Add 2nd byte
A2
ADR[8:1]
Reserved for future purposes
Reserved for future purposes
Sr
Reserved for different bus
10-bit slave addressing
General call address
11110+ADR10+ADR9
Slave Add 1st 7bits
DESCRIPTION
format
A2
.
Data
Freescale Semiconductor
R/W
1
A3
A3
Data
A4