S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 155

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

If the interrupt source is unknown (for example, in the case where an interrupt request becomes inactive
after the interrupt has been recognized, but prior to the CPU vector request), the vector address supplied
to the CPU will default to that of the spurious interrupt vector.
4.4.3
The INT module supports three system reset exception request types (please refer to the Clock and Reset
generator module for details):
4.4.4
The priority (from highest to lowest) and address of all exception vectors issued by the INT module upon
request by the CPU is shown in
1
2
3
Freescale Semiconductor
(Vector base + 0x00F0–0x0082) Device specific I bit maskable interrupt sources (priority determined by the low byte of the
16 bits vector address based
D2D error interrupt on MCUs featuring a D2D initiator module, otherwise XIRQ pin interrupt
D2D interrupt on MCUs featuring a D2D initiator module, otherwise IRQ pin interrupt
1. Pin reset, power-on reset or illegal address reset, low voltage reset (if applicable)
2. Clock monitor reset request
3. COP watchdog reset request
(Vector base + 0x00F8)
(Vector base + 0x00F6)
(Vector base + 0x00F4)
(Vector base + 0x00F2)
(Vector base + 0x0080)
Vector Address
0xFFFC
0xFFFE
0xFFFA
Reset Exception Requests
Exception Priority
Care must be taken to ensure that all interrupt requests remain active until
the system begins execution of the applicable service routine; otherwise, the
exception request may not get processed at all or the result may be a
spurious interrupt request (vector at address (vector base + 0x0080)).
1
Pin reset, power-on reset, illegal address reset, low voltage reset (if applicable)
Clock monitor reset
COP watchdog reset
Unimplemented opcode trap
Software interrupt instruction (SWI) or BDM vector request
X bit maskable interrupt request (XIRQ or D2D error interrupt)
IRQ or D2D interrupt request
vector address, in descending order)
Spurious interrupt
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Table 4-4. Exception Vector Map and Priority
Table
4-4.
NOTE
3
Source
2
Interrupt Module (S12SINTV1)
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