S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 273

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.4.6
7.4.6.1
This mode is the default mode after System Reset or Power-On Reset.
The Bus Clock is based on the PLLCLK, the reference clock for the PLL is internally generated (IRC1M).
The PLL is configured to 64 MHz VCOCLK with POSTDIV set to 0x03. If locked (LOCK=1) this results
in a PLLCLK of 16 MHz and a Bus Clock of 8 MHz. The PLL can be re-configured to other bus
frequencies.
The clock sources for COP and RTI are based on the internal reference clock generator (IRC1M).
7.4.6.2
In this mode, the Bus Clock is based on the PLLCLK as well (like PEI). The reference clock for the PLL
is based on the external oscillator. The adaptive spike filter and detection logic which uses the VCOCLK
to filter and qualify the external oscillator clock can be enabled.
The clock sources for COP and RTI can be based on the internal reference clock generator or on the
external oscillator clock.
This mode can be entered from default mode PEI by performing the following steps:
Since the adaptive spike filter (filter and detection logic) uses the VCOCLK to continuously filter and
qualify the external oscillator clock, loosing PLL lock status (LOCK=0) means loosing the oscillator status
information as well (UPOSC=0).
The impact of loosing the oscillator status in PEE mode is as follows:
Application software needs to be prepared to deal with the impact of loosing the oscillator status at any
time.
Freescale Semiconductor
1. Configure the PLL for desired bus frequency.
2. Optionally the adaptive spike filter and detection logic can be enabled by calculating the integer
3. Enable the external oscillator (OSCE bit).
4. Wait for the PLL being locked (LOCK = 1) and the oscillator to start-up and additionally being
5. Clear all flags in the CPMUFLG register to be able to detect any future status bit change.
6. Optionally status interrupts can be enabled (CPMUINT register).
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value for the OSCFIL[4:0] bits and setting the bandwidth (OSCBW) accordingly.
qualified if the adaptive spike filter is enabled (UPOSC =1).
The PLLCLK is derived from the VCO clock (with its actual frequency) divided by four until the
PLL locks again.
System Clock Configurations
PLL Engaged Internal Mode (PEI)
PLL Engaged External Mode (PEE)
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
273