S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 171

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.4.5
Hardware and firmware BDM commands start with an 8-bit opcode followed by a 16-bit address and/or a
16-bit data word, depending on the command. All the read commands return 16 bits of data despite the
byte or word implication in the command name.
For hardware data read commands, the external host must wait at least 150 bus clock cycles after sending
the address before attempting to obtain the read data. This is to be certain that valid data is available in the
BDM shift register, ready to be shifted out. For hardware write commands, the external host must wait
150 bus clock cycles after sending the data to be written before attempting to send a new command. This
is to avoid disturbing the BDM shift register before the write has been completed. The 150 bus clock cycle
delay in both cases includes the maximum 128 cycle delay that can be incurred as the BDM waits for a
free cycle before stealing a cycle.
For firmware read commands, the external host should wait at least 48 bus clock cycles after sending the
command opcode and before attempting to obtain the read data. The 48 cycle wait allows enough time for
the requested data to be made available in the BDM shift register, ready to be shifted out.
For firmware write commands, the external host must wait 36 bus clock cycles after sending the data to be
written before attempting to send a new command. This is to avoid disturbing the BDM shift register
before the write has been completed.
Freescale Semiconductor
BDM Command Structure
8-bit reads return 16-bits of data, only one byte of which contains valid data.
If reading an even address, the valid data will appear in the MSB. If reading
an odd address, the valid data will appear in the LSB.
16-bit misaligned reads and writes are generally not allowed. If attempted
by BDM hardware command, the BDM ignores the least significant bit of
the address and assumes an even address from the remaining bits.
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Background Debug Module (S12SBDMV1)
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