S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 572

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

48 KByte Flash Module (S12FTMRC48K1V1)
16.3.2.1
The FCLKDIV register is used to control timed events in program and erase algorithms.
All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the
writability of the FDIV field.
572
FDIVLCK
FDIV[5:0]
FDIVLD
Address
Offset Module Base + 0x0000
Reset
& Name
0x0012
0x0013
FRSV6
FRSV7
Field
5–0
7
6
W
R
FDIVLD
Clock Divider Loaded
0 FCLKDIV register has not been written since the last reset
1 FCLKDIV register has been written since the last reset
Clock Divider Locked
0 FDIV field is open for writing
1 FDIV value is locked and cannot be changed. Once the lock bit is set high, only reset can clear this bit and
Clock Divider Bits — FDIV[5:0] must be set to effectively divide BUSCLK down to 1 MHz to control timed events
during Flash program and erase algorithms.
BUSCLK frequency. Please refer to
Flash Clock Divider Register (FCLKDIV)
0
7
W
W
R
R
restore writability to the FDIV field.
The FCLKDIV register must never be written to while a Flash command is
executing (CCIF=0). The FCLKDIV register is writable during the Flash
reset sequence even though CCIF is clear.
= Unimplemented or Reserved
7
0
0
FDIVLCK
Figure 16-4. FTMRC48K1 Register Summary (continued)
0
6
Figure 16-5. Flash Clock Divider Register (FCLKDIV)
= Unimplemented or Reserved
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
6
0
0
Table 16-6. FCLKDIV Field Descriptions
0
5
Section 16.4.3, “Flash Command Operations,”
5
0
0
CAUTION
Table 16-7
0
4
Description
4
0
0
shows recommended values for FDIV[5:0] based on the
0
3
FDIV[5:0]
3
0
0
0
2
2
0
0
for more information.
Freescale Semiconductor
0
1
1
0
0
0
0
0
0
0