S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 765

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

0x0010–0x0017 Module Mapping Control (MMC) Map 2 of 2
0x0018–0x001B Miscellaneous Peripheral
1. Refer to Part ID assignments in the device description section for a full list of MC9S12HY/HAPart ID values.
0x001C–0x001F Port Integration Module (PIM) Map 3 of 6
Freescale Semiconductor
Address
Address
Address
0x00010
0x0016-
0x001C
0x001D
0x0011
0x0012
0x0013
0x0014
0x0015
0x0017
0x0018
0x0019
0x001A
0x001B
0x001E
0x001F
PARTIDH
PARTIDL
ECLKCTL
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Register
DIRECT
PPAGE
IRQCR
Name
Name
Name
(1)
1
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
W
W
W
W
W
W
W
R
R
R
R
R
R
R
NECLK
IRQE
Bit 7
Bit 7
DP15
Bit 7
0
0
0
1
0
0
0
0
0
0
0
0
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
IRQEN
Bit 6
Bit 6
DP14
0
0
0
0
0
0
0
6
0
0
0
0
0
0
XIRQEN
DIV16
Bit 5
Bit 5
DP13
0
0
0
0
0
0
5
0
0
0
0
0
0
EDIV4
Bit 4
Bit 4
DP12
0
0
1
0
0
0
0
4
0
0
0
0
0
0
EDIV3
DP11
Bit 3
Bit 3
PIX3
0
0
1
0
0
0
0
3
0
0
0
0
0
EDIV2
DP10
Bit 2
Bit 2
PIX2
0
0
0
0
0
0
0
2
0
0
0
0
0
Detailed Register Address Map
EDIV1
Bit 1
Bit 1
PIX1
DP9
0
0
1
0
0
0
0
1
0
0
0
0
0
EDIV0
Bit 0
Bit 0
Bit 0
PIX0
DP8
0
0
0
0
0
0
0
0
0
0
0
0
765