S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 74

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
1
Port Integration Module (S12HYPIMV1)
2.3.7
2.3.8
74
Address 0x0004 (PRR) to 0x0007 (PRR)
Address 0x000C (PRR)
Read: Always reads 0x00
Write: Unimplemented
Read:Anytime in single-chip modes.
Write:Anytime, except BKPUE which is writable in Special Single-Chip Mode only.
DDRB
Field
Reset
Reset
7-0
W
W
R
R
Port B Data Direction—
This bit determines whether the associated pin is an input or output.
If corresponding LCD segment is enabled, it will be forced as input/output disabled
1 Associated pin is configured as output
0 Associated pin is configured as input
PIM Reserved Register
Ports A, B, BKGD pin Pull Control Register (PUCR)
0
0
0
0
7
7
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTA, PTB registers, when changing the
DDRA,DDRB register.
= Unimplemented or Reserved
= Unimplemented or Reserved
Figure 2-6. Ports AB, BKGD pin Pull Control Register (PUCR)
BKPUE
0
0
1
6
6
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Table 2-7. DDRB Register Field Descriptions
Figure 2-5. PIM Reserved Register
0
0
0
0
5
5
NOTE
0
0
0
0
4
4
Description
3
0
0
3
0
0
0
0
0
0
2
2
Freescale Semiconductor
PUPBE
Access: User read/write
0
0
1
1
1
Access: User read
PUPAE
0
0
1
0
0
1
1