CX28344 Conexant, CX28344 Datasheet - Page 101

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

CX28342/3/4/6/8 Data Sheet
2.2.8
28348-DSH-001-B
Far-End Alarm and Control Channel Reception
The FEAC channel resides on the C13 bit of DS3 C-bit Parity frames. There are three
ways to access FEAC contents: through the data stream (marked with other overheads
by RXGAPCK), through the data stream marked by REXTCK, or through a
register-based microprocessor interface.
section describes the details of the third.
FEAC messages are in the form of 16-bit code words, with a pattern of
0xxxxxx011111111 (right-to-left). The code word overhead are the 10 fixed bits. The
code word proper are the six x bits. The entire 16 bits are represented as the complete
code word pattern. When no alarm or control signal is present, the channel carries an
all-1s (idle) pattern. Internal circuitry (Receive FEAC [RFEAC] block) provides logic
and a register for implementing FEAC message identification. As this channel is
undefined in DS3 M13/M23 and E3 modes, the RFEAC is automatically disabled in
these modes.
The RFEAC comes in two modes (selectable through the FEACSin field of the
Feature3 Control register), single code word detection (makes no assumptions about
FEAC messages repetitions) and multiple code word detection (assumes each FEAC
message is repeated at least 10 times).
In single code word detection, a valid code word is detected when one complete code
word pattern is located.
In multiple code word detection, a valid code word is detected when nine complete
code word patterns with the same code word proper are located, using the following
algorithm F:
NOTE:
F1. [Initiation] Locate a complete code word pattern, store its code word
F2. [Tentative] Locate another complete code word pattern and compare its
F3. [Tentative and Alternative] Locate another complete code word pattern and
F4. [Alternative] Compare cp3 with the alternative code word:
F5. [Possible Termination] if counter 9 declare a valid code word and end
proper (cp1) in a 6-bit register (termed the tentative code word), set a 4-bit
counter to 1, and go to step F2
code word proper (cp2) with the tentative code word:
compare its code word proper (cp3) with the tentative code word:
algorithm, if not go to step F2
a. if identical, add 1 to the counter, and go to step F5
b. if not, store cp2 in another 6-bit register (termed the alternative code
a. if identical, add 2 to the counter (for cp2 and cp3), and go to step F5
b. if not, go to step F4
a. if identical, store the alternative code word in the tentative code
b. if not, store the alternative code word in the tentative code word
Mindspeed Technologies™
When comparing code word propers, the number of bits differing between the two is
of no importance, just their identity or lack of identity.
word) and go to step F3.
word register, set the counter to 2 (for cp2 and cp3) and return to
step F2
register, set the counter to 1, store cp3 in the alternative code word
register, and return to step F3
Section 2.
discusses the first two. This
Functional Description
2
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