CX28344 Conexant, CX28344 Datasheet - Page 7

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

Figures
28348-DSH-001-B
Figure 1-1.
Figure 1-2.
Figure 1-3.
Figure 1-4.
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 2-4.
Figure 2-5.
Figure 2-6.
Figure 2-7.
Figure 2-8.
Figure 2-9.
Figure 2-10.
Figure 2-11.
Figure 2-12.
Figure 2-13.
Figure 2-14.
Figure 2-15.
Figure 2-16.
Figure 2-17.
Figure 2-18.
Figure 2-19.
Figure 4-1.
Figure 4-2.
Figure 4-3.
Figure 4-4.
Figure 4-5.
Figure 4-6.
Figure 4-7.
Figure 4-8.
Figure 4-9.
Figure 4-10.
Figure 4-11.
Figure 4-12.
CX28342 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
CX28343 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
CX28344 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
CX28346/8 Pin Assignments (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
Functional Block Diagram of a Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Transmitter Line Side Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Tx System Side External Overhead Insertion (DS3 FEBE-only example) . . . . . . . . . . . . . . . 2-4
DS3 System Side Transmission when TXSY is Externally Provided . . . . . . . . . . . . . . . . . . 2-6
DS3 System Side Transmission Unit when TXSY is Used as an Overhead Indication Bit . . 2-6
DS3 System Side Transmit when TXSY is Input Signal (Frame Start) . . . . . . . . . . . . . . . . . 2-7
E3-G.751 Transmit Mode when TXSY is Frame Start Sync Output Signal . . . . . . . . . . . . . . 2-8
E3-G.751 Transmit Mode where TXSY is an Overhead Indicator Output Signal . . . . . . . . . 2-8
E3-G751 Mode where TXSY is an Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
E3-G.832 Mode where TXSY is an Output Signal Indicating Frame Start Sync . . . . . . . . . . 2-9
TXSY Transmitter System Side Signal (E3-G.832) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
TXSY Transmitter System Side Signal (E3-G.832) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Line Coding Error Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
Receiver Line Side Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
Receiver System Side Outputs [RXGAPCK] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37
Receiver System Side Outputs [REXTCK] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38
Receiver System Side Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39
VCO Output Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40
Loopback Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62
Power Ramp Sequence of VDDx and VDDOx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Input Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Line Side Receiver Input Data Setup/Hold Timing (1 = tsu [setup time]; 2 = thld [hold time]) .
4-5
Line Side Transmitter Output Data Timing (1 = tpd [propogation delay]) . . . . . . . . . . . . . . 4-5
System-Side Transmitter Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
System-Side Receiver Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Intel Asynchronous Read Cycle (MOTO* = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Intel Asynchronous Write Cycle (MOTO* = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Motorola Asynchronous Read Cycle (MOTO* = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
Motorola Asynchronous Write Cycle (MOTO* = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Mechanical Specification for 144-pin ETQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Mindspeed Technologies™
vii