CX28344 Conexant, CX28344 Datasheet - Page 95

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

CX28342/3/4/6/8 Data Sheet
2.2.7
28348-DSH-001-B
Terminal Data Link Reception
The terminal data link channel (DL) resides on the C5 bits of DS3 C-bit Parity frames,
which is approximately 28.195 Kbps (3/4760 bits at 44.736 Mbps). On the N-bit of
E3-G.751 frames, it is approximately 22.375 Kbps (1/1536 bits at 34.368 Mbps). On
the NR or GC (but not both) bytes of E3-G.832 frames, it is approximately 64 Kbps
(1/537 bytes at 34.368 Mbps). The DL contents are generally available via one or
more of three routes, the data stream (marked with other overheads by RXGAPCK),
marked by REXTCK, or through a FIFO-buffered microprocessor interface; the first
two are specified in
The internal circuitry [Receive Data Link (RDL) block] provides logic and FIFO for
implementing LAPD/HDLC terminal data link reception according to ITU-T Q.921
and ISO/IEC 3309 standards. The logic is responsible for flag and abort sequence
detection, 16-bit frame check sequence (FCS) checking and transparency zero
removal, and managing the internal FIFO. Each of the channels contains a 128-byte
Receive Data Link FIFO buffer, distinct from the Transmit Data Link FIFO buffer, to
reduce the amount of intervention required from the system in accessing the data link
contents. FIFO buffer contents are accessed via the microprocessor interface either in
interrupt-driven mode, using maskable interrupts to synchronize data flow into and
out of the FIFO buffer, or in status-polling mode.
The RDL FIFO buffer contains two types of information, data bytes and status bytes.
Data bytes are the actual data extracted from the DL channel (all flag-bounded bytes
except flag and abort sequences and zeros for transparency). Status bytes contain
additional information qualifying the data bytes following them.
A data block within the FIFO buffer is one status byte followed by 0 to 127 data
bytes.
When a new block starts, the RDL reserves one byte for status and then fills data
bytes, as required, until the end of the block. At the end, status information is written
into the reserved byte and a new block is started.
A block terminates and a new one starts in conjunction with one of the following:
!
!
!
Before the status byte is read from the RxMsgByte Status register, the user must read
the RDL Status register and get the RxGoodBlk field value. This bit defines the type
of the status byte to be read from the RxMsgByte Status register.
A FIFO near-full interrupt
A message received interrupt
A FIFO overrun interrupt
Mindspeed Technologies™
Section 2.
this section describes the details of the third mode.
Functional Description
2
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