CX28344 Conexant, CX28344 Datasheet - Page 131

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

CX28342/3/4/6/8 Data Sheet
Default after reset: 00(h)
Direction: Read/Write
Modification: Bits 0–2, 4: static, bits 6–7: dynamic, bit 5: dynamic for DL (G.832) and static for reserved C-bits
(DS3), bit 3: dynamic for Cj and static for FEBE
DLMod[2:0]
Table 3-3. DS3-C Bit Parity/E3-G.751 Mode Field Interpretation
28348-DSH-001-B
DLMod[2]
DLMod[2]
7
0
1
1
DLMod[1]
Data Link Mode—This field is interpreted differently in different working modes. In E3-
G.832 mode, it is a three-bit field that determines the source of NR and GC bytes. In E3-
G.751, only DLMod [2:1] determines the source of the N-bit, while DLMod [0] has no effect.
In DS3-C, Bit Parity mode DLMod [2:1] determines the source of the data link (Cb5), and
DLMod [0] determines the source of the reserved C-bits. In DS3-M13/M23, this field has no
effect.
Tables 3-3
6
DLMod[1]
Transmit Overhead Insertion Control Registers
The Transmit Overhead Insertion Control registers are provided to enable insertion of
different overhead fields from different sources listed below:
!
!
!
!
Transmit Overhead Insertion1 Control Register (CR09i)
NOTE:
NOTE:
X
0
1
and
Internal automatic generation
Internal registers programmed by the microprocessor
The system via the data stream
The system via TEXT pin
DLMod[0]
3-4
5
detail the interpretation of this field in the different modes.
Transmit Data Link circuit is disabled, and the framer automatically sends the all-1s
pattern on Cb5 bits/N-bit.
Data link data is inserted through the Transmit Data Link FIFO buffer and is processed
by the internal HDLC circuit.
Data link data is inserted through the TEXT pin and is unaffected by the internal HDLC
circuit.
Mindspeed Technologies™
Not all the sources are available for every overhead field in every mode.
Some of the control bits have no effect in a specific mode. Some of the
bits have multiple meanings, it depends on the working mode.
If the system wants to change the source of the data link (i.e., internal
FIFO to TEXT pin), it must first disable the data link and then enable it
by setting the appropriate mode. Another example is that when
changing the type of byte processed by the internal HDLC circuit (NR
to GC or vice versa) in E3-G.832 mode, the data link must be disabled
first for both (by writing 0 to all three bits).
AutoRAI
4
ExtFEBE/Cj
3
Description
ExtCP/TR
2
ExtFEAC/PD
1
ExtDat
0
Registers
3
-
19