CX28344 Conexant, CX28344 Datasheet - Page 51

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

CX28342/3/4/6/8 Data Sheet
28348-DSH-001-B
When bit TxOvhMrk is set to 0, TXSY output functions as a frame start
synchronization signal. The frame data bits provided to the transmitter on TXDATI
are expected to be synchronized to the TXSY indication of frame start. After enabling
the framer in this mode, the sync signal is automatically provided on TXSY output. In
this mode the sync output signal on TXSY transitions from low to high and from the
last bit of the frame to the first bit of the next frame (sampled as high with the first bit
of the next frame). When TxOvhMrk bit is set to 1, TXSY output functions as an
overhead indication signal. TXSY at this mode is low during all Overhead bits
(including during Justification Control bits and Stuff Opportunity bits) and is high
during all payload bits.
If the system does not require TXSY for its operation, it should set it as an output
where automatic synchronization is provided all the time.
Transmit Operation in DS3 Mode
In DS3 mode, TXCKI is connected to a 44.736 MHz clock.
If the TXSY signal is provided externally, it should have a low-to-high transition from
the last bit of the M-frame to the first bit of the next frame. If the TXSY is provided
internally and used as a frame start synchronization signal (bit TxOvhMrk is set to 0
at Feature 2 Control register), it has a low-to-high transition from the last bit of the M-
frame to the next bit of the next frame. The TXSY output returns to low after M3 bit
of subframe 7. If the TXSY signal is used as an overhead indication output signal (bit
TxOvhMrk is set to 1 at Feature 2 Control register), TXSY is low during all Overhead
bits positions, and high during data bits position regardless of the Overhead bits
source.
Figures 2-4
the overheads are inserted with payload.
Figure 2-4
synchronization output signal. In this setting the TXSY signal transitions from low to
high at the last rising edge of TXCKI clock and before the X1 bit is sampled in on the
next falling edge of TXCKI. The TXSY signal goes low again at the rising of TXCKI
clock, and after M3 bit of subframe 7 is entered on TXDATI, it remains low during
the rest of subframe 7.
NOTE:
illustrates the behavior of TXSY, when it is used as a frame start
through
Mindspeed Technologies™
After reset, this pin has a high-Z value until it is set to be used as an input or an
output.
2-6
illustrate the transmitter timing for DS3 mode where none of
Functional Description
2
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5