CX28344 Conexant, CX28344 Datasheet - Page 72

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

Functional Description
2.1.3.4
2-26
Sending Message Using the FIFO—Normal Operation
In normal operation when the TDL FIFO buffer is empty, the TDL circuitry generates
IDLE flags. When the system has a message to transmit on the data link, it should
write it to the FIFO buffer, one byte each time, by writing all data bytes (except the
last message byte) to the low address of the Transmit Data Link Message Byte
register (TxDLMsg [7:0]). The last byte of the message should be written to the high
address of the Transmit Data Link Message Byte register indicating to the TDL circuit
that it is the last byte of the message (EOM byte). After EOM, if the FIFO buffer is
not FULL, another message can be written following the last EOM byte.
There is no limit to the length of each message, and the FIFO buffer can contain more
than one message written to it at a time.
EMPTY and FULL status bits are provided to help the system evaluate FIFO’s
content and message transmission status, Near-Empty Threshold and Status,
Transmitted Message Status indication and interrupt. With the help of these data bits,
the system can control its accesses to optimally use the TDL FIFO buffer with
minimum accesses.
The internal logic terminates sending FLAG messages as soon as a new message byte
is written to the FIFO buffer. The new message is sent until an EOM byte is
encountered, which is followed by sending FCS (if enabled) and two FLAG
sequences. After sending the closing FLAG of each message, an indication of
transmitted message and an interrupt (if enabled) is provided. The next message
immediately starts if the FIFO buffer is not empty. If the last transmitted octet was an
EOM, FLAG sequences continue to be generated and transmitted.
From the system point of view there are two TDL modes, Interrupt Driven mode and
Polling mode.
Interrupt Driven Mode
Unmasking at least one FIFO-related interrupt (Near-Empty, Underrun, or Message
Transmitted) enables interrupt driven mode.
Once an interrupt occurs, the microprocessor should read the Source Channel Status
register to identify which framer is the interrupt’s originator, then read the framer’s
Interrupt Source (i) Status register to identify which block raised the interrupt at the
particular framer (TDL in this case—bit TxDLFEACItr is high). It then reads the
Transmit Data Link FEAC Status register to identify the type of interrupt (Underrun,
Near-Empty, or Message Transmitted).
handling for normal operation is to read the Transmit Data Link FEAC Status register as
the interrupt occurs. If the TDL Near-Empty indication is set, a new block of data bytes
are written and transmitted (maximum 128 Near-Empty threshold bytes to safely fill the
FIFO buffer). After servicing this interrupt, the system waits for another interrupt.
Polling Mode
Polling mode is effective when TDL function interrupts are masked. In Polling mode,
the service routine are executed based on timers. Here, after writing a message byte or
a message block of several bytes, the service routine shall wait for N milliseconds
(based on the data link rate and the block size written) and poll or sample the Transmit
Data Link FEAC Status register to check whether the FIFO buffer is empty or near
empty, and if so, write another block. In this mode, TDL status is read before writing
to the FIFO buffer.
There are many available settings and methods handling of interrupts. The proposed
Mindspeed Technologies™
CX28342/3/4/6/8 Data Sheet
28348-DSH-001-B