CX28344 Conexant, CX28344 Datasheet - Page 86

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

Functional Description
2.2.3
Figure 2-18. VCO Output Signal Timing
2-40
LINECK
÷ 16
RXCKI
÷16
VCO
Output
Clock Dejitter FIFO
The receiver circuit contains a 16-bit FIFO buffer immediately following the
bipolar-to-unipolar decoding logic (or the unipolar input in unipolar-mode) to provide
jitter elasticity up to ± 5 line clock cycles. The data stream is clocked into the FIFO
buffer with the incoming LINECK clock. The data stream is clocked out of the FIFO
buffer and into the remaining receiver circuitry by RXCKI, which is a dejittered
version of LINECK. The FIFO circuit provides a Voltage-Controlled Oscillator
(VCO) control signal to indicate the phase relationship of FIFO input and output
clocks. Both clocks are divided by 16 internally to derive the VCO output, as
illustrated in
producing the smoothed RXCKI.
The FIFO circuit is bypassed, and all receiver circuitry is clocked with LINECK if the
RxFIFEn field of the Feature5 Control register is cleared; in this case RXCKI should
be tied to ground.
See Appendix A for analysis and reference design.
NOTE:
Mindspeed Technologies™
Figure
The VCO signal is active all the time, even during channel disable and reset.
2-18. This signal can be used to control the clock recovery circuit
CX28342/3/4/6/8 Data Sheet
28348-DSH-001-B
100542_021