CX28344 Conexant, CX28344 Datasheet - Page 79

• Manufacturer Part Number: CX28344
• Description: (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer
• Manufacturer: Conexant

CX28342/3/4/6/8 Data Sheet
2.1.5.3
Table 2-6. Setting the Error Insertion1 Control Register in E3-G.832 Mode
2.1.5.4
28348-DSH-001-B
Framing Error
(FA error)
BIP-8 parity
RDI
REI (FEBE)
Error
FrmErrF
ParErr
YelErr
FEBEErr
Bit
E3-G.832 Mode
In the E3-G.832 mode of operation, setting bits at the Error Insertion1 Control register
can generate errors listed in
Line Coding Errors
In all basic modes of operation, line code errors can be forced when the transmitter
line side is operating in AMI or rail (HDB3/B3ZS encoding) mode.
In AMI or rail mode, a bipolar violation (BPV) can be inserted by setting the
LCVBPV bit in Error Insertion2 Control register. The next 11 arriving after the bit is
set is changed to 1V (this restriction, rather than just reversing the next 1, prevents
inadvertently creating a zero-substitution sequence). Then, the encoding circuitry
adjusts itself to the reversed signal, causing the following output to be opposite the
one that would have been produced had this error not been introduced; otherwise each
error insertion would result in two consecutive BPVs.
example.
In rail mode, an illegal substitution (IllSub) can be inserted by setting the LCVIllSub bit
in Error Insertion2 Control register. The next 000 (in DS3) or 0000 (in E3) arriving after
the bit is set, is reversed (00V to 10V or vice versa in DS3; 000V to 100V or vice versa
in E3). Then the encoding circuitry adjusts itself to the reversed signal, causing the
following output to be the reverse of the one that would have been produced had this
error not been introduced; otherwise each error insertion would also result in a BPV .
NOTE:
Set to
Mindspeed Technologies™
Error insertion can be performed by the system only on Overhead bits that are set to
be automatically generated or taken from a register. Setting error insertion on
Overhead bits where the source is set to be from TEXT pin, or inserted with payload,
produces undefined results.
1
1
1
1
Transmission of one framing bit error. This causes one bit of the next FA
Transmission of a single incorrect bit in the next BIP-8 sequence by
Transmission of the opposite value to the expected one (by automatic
sequence to be inverted.
inverting it before transmission.
Transmission of the opposite value of RDI-bit than expected or set. The
next transmitted RDI-bit is cleared to 0 if an RDI should be transmitted,
and set to 1 if RDI is not expected (done by inverting the next RDI-bit
before transmission).
generation or its inserted value from external pin or with payload) at the
next MA REI-bit position. This is done by inverting the next transmitted
MA REI-bit.
Description
Figure 2-13
illustrates an
Functional Description
2
-
33